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F81867 dec, 2011 v0.12p F81867 6 uarts super io with 128 bytes fifo and power saving functions release date: dec, 2011 version: v0.12p
F81867 dec, 2011 v0.12p F81867 datasheet revision history version date page revision history v0.10p 2011/7/13 - preliminary v0.11p 2011/8/24 - made clarification and correction add register section 7 v0.12p 2011/12/12 - 1. made clarification and correction 2. i2c protocol select ? index efh, bit 3-0 3. update all register reset type 4. add multifunction registers 5. add kbc/acpi related description/timing/ ovp/ amd tsi/intel peci 3.0/ (see section 6.5 to 6.11) 6. update application circuit (add soft start circuit to 5vsb) please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support app liances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. customers using or selling these products for use in such applications do so at their own risk and agr ee to fully indemnify fintek for any damages resulting from such improper use or sales.
F81867 dec, 2011 v0.12p table of content 1. general de scription ...................................................................................................... 1 0 2. feat ures ................................................................................................................... .... 10 3. block diagram .............................................................................................................. 15 4. pin conf igurat ion .......................................................................................................... 16 5. pin de scription ............................................................................................................ . 17 5.1 power pin ................................................................................................................. .............. 17 5.2 clock ..................................................................................................................... ................. 18 5.3 lpc interface ............................................................................................................. ............ 18 5.4 fdc ....................................................................................................................... ................. 18 5.5 parallel port (lpt port) .................................................................................................. ........ 20 5.6 hardware monitor ................................................................................................................... 22 5.7 kbc function .............................................................................................................. ........... 23 5.8 acpi, erp ................................................................................................................. ............ 24 5.9 uart, sir ................................................................................................................. ............. 26 6. function de scription ..................................................................................................... 2 9 6.1 power on strapping option ................................................................................................. ... 29 6.2 fdc ....................................................................................................................... ................. 29 6.3 parallel port ............................................................................................................................ 30 6.4 hardware monitor ................................................................................................................... 33 6.4.1 general descr iption ........................................................................................ 33 6.4.2 hardware monitor de vice regi sters ............................................................... 46 6.4.2.1configuration setting .................................................................................................. ......... 46 6.4.2.2peci/tsi/i2c setting ................................................................................................... ........ 47 tsi or ibex control register ? index 08h ................................................................................... 47 i2c address control register ? index 09h .................................................................................... 47 peci, tsi, ibex, beta register ? index 0ah ................................................................................ 48 cup socket select register ? index 0bh ..................................................................................... 48 tcc register ? index 0ch ............................................................................................................ 48 tsi offset register ? index 0dh ................................................................................................... 49 configuration register ? index 0fh .............................................................................................. 49 tsi temperature 0 ? index e0h ...................................................................................................... 49 tsi temperature 1 ? index e1h ...................................................................................................... 49 tsi temperature 2 low byte ? index e2h ...................................................................................... 5 0 tsi temperature 2 high byte ? index e3h ..................................................................................... 5 0
F81867 dec, 2011 v0.12p tsi temperature 3 ? index e4h ...................................................................................................... 50 tsi temperature 4 ? index e5h ...................................................................................................... 50 tsi temperature 5 ? index e6h ...................................................................................................... 51 tsi temperature 6 ? index e7h ...................................................................................................... 51 tsi temperature 7 ? index e8h ...................................................................................................... 51 i2c data buffer 9 ? index e9h ................................................................................................. ....... 51 block write count register ? index ech ........................................................................................ 52 i2c command byte/tsi command byte ? index edh ................................................................... 52 i2c status ? index eeh ........................................................................................................ .......... 52 i2c protocol select ? index efh ............................................................................................... ..... 53 6.4.2.3peci 3.0 & temperature setting ......................................................................................... 53 peci 3.0 command and register .................................................................................................. 53 peci configuration register ? index 40h ..................................................................................... 53 peci master control register ? index 41h ................................................................................... 53 peci master status register ? index 42h .................................................................................... 54 peci master data0 register ? index 43h ................................................................................... 54 peci master data1 register ? index 44h ................................................................................... 54 peci master data2 register ? index 45h ................................................................................... 54 peci master data3 register ? index 46h ................................................................................... 55 peci master data4 register ? index 47h ................................................................................... 55 peci master data5 register ? index 48h ................................................................................... 55 peci master data6 register ? index 49h ................................................................................... 55 peci master data7 register ? index 4ah ................................................................................... 55 peci master data8 register ? index 4bh ................................................................................... 55 peci master data9 register ? index 4ch ................................................................................... 55 peci master data10 register ? index 4dh ................................................................................. 56 peci master data11 register ? index 4eh ................................................................................. 56 peci master data12 register ? index 4fh ................................................................................. 56 hwm manual control register1 ? index 50h ............................................................................... 56 hwm manual control status register 1 ? index 51h .................................................................... 56 hwm manual control status register 2 ? index 52h .................................................................... 57 hwm raw data register 1 ? index 55h ....................................................................................... 57 hwm raw data register 2 ? index 56h ....................................................................................... 57 temperature register ..................................................................................................................... 57 temperature pme# enable register ? index 60h ......................................................................... 57 temperature interrupt status register ? index 61h ...................................................................... 58 temperature real time status register ? index 62h ................................................................... 58
F81867 dec, 2011 v0.12p temperature beep enable register ? index 63h ......................................................................... 59 t1 ovt and high limit temperature select register ? index 64h ............................................... 59 ovt and alert output enable register 1 ? index 66h .................................................................. 60 temperature sensor type register ? index 6bh .......................................................................... 60 temp1 limit hystersis select register ? index 6ch .................................................................... 60 temp2 and temp3 limit hystersis select register ? index 6dh ................................................ 60 diode open status register ? index 6fh .................................................................................. 61 temperature ? index 70h- 8dh ..................................................................................................... 61 t1 slope adjust register ? index 7fh .......................................................................................... 62 temperature filter select register ? index 8eh ............................................................................ 62 6.4.2.4voltage setting ........................................................................................................ ............ 63 voltage-protect shut down enable register ? index 10h ............................................................ 63 voltage-protect status register ? index 11h ................................................................................ 63 voltage-protect configuration register ? index 12h ..................................................................... 63 voltage1 pme# enable register ? index 14h ............................................................................... 64 voltage1 interrupt status register ? index 15h ............................................................................ 64 voltage1 exceeds real time status register 1 ? index 16h ........................................................ 64 voltage1 beep enable register ? index 17h ............................................................................... 65 voltage protection power good select register ? index 3fh ...................................................... 65 voltage reading and limit ? index 20h- 3ah ................................................................................... 65 6.4.2.5fan control setting..................................................................................................... ......... 66 fan pme# enable register ? index 90h ...................................................................................... 66 fan interrupt status register ? index 91h ................................................................................... 66 fan real time status register ? index 92h ................................................................................. 66 fan beep# enable register ? index 93h .................................................................................... 67 fan type select register ? index 94h (fan_prog_sel = 0) ................................................... 67 fan1 base temperature register ? offset 94h (fan_prog_sel = 1) ........................................ 68 fan1 temperature adjustment rate register ? index 95h (fan_prog_sel = 1)..................... 68 fan mode select register ? index 96h (fan_prog_sel = 0) .................................................. 69 fan mode select register ? index 96h (fan_prog_sel = 1) .................................................. 70 faster fan filter control register ? index 97h ............................................................................. 70 auto fan1 and fan2 boundary hystersis select register ? index 98h ...................................... 71 auto fan3 boundary hystersis select register ? index 99h ....................................................... 71 fan3 control register ? index 9ah............................................................................................... 71 auto fan up speed update rate select register ? index 9bh (fan_prog_sel = 0) .............. 72 auto fan down speed update rate select register ? index 9bh (fan_prog_sel = 1) .......... 72 fan1 and fan2 start up duty-cycle/voltage ? index 9ch ............................................ 73
F81867 dec, 2011 v0.12p fan3 start up duty-cycle/voltage ? index 9dh ............................................................. 73 fan programmable duty-cycle/voltage loaded after power-on ? index 9eh 74 fan fault time register ? index 9fh ............................................................................................ 74 a. fan1 index a0h~afh ......................................................................................................... ... 74 vt1 boundary 1 temperature ? index a6h ......................................................................... 75 vt1 boundary 2 temperature ? index a7 ........................................................................... 75 vt1 boundary 3 temperature ? index a8h ......................................................................... 76 vt1 boundary 4 temperature ? index a9 ........................................................................... 76 fan1 segment 1 speed count ? index aah ......................................................................... 76 fan1 segment 2 speed count ? index abh ......................................................................... 76 fan1 segment 3 speed count register ? index ach ........................................................... 77 fan1 segment 4 speed count register ? index adh ........................................................... 77 fan1 segment 5 speed count register ? index aeh ........................................................... 77 fan1 temperature mapping select ? index afh ........................................................................... 77 b. fan2 index b0h~bfh ......................................................................................................... ... 78 vt2 boundary 1 temperature ? index b6h ......................................................................... 79 vt2 boundary 2 temperature ? index b7 ........................................................................... 79 vt2 boundary 3 temperature ? index b8h ......................................................................... 80 vt2 boundary 4 temperature ? index b9 ........................................................................... 80 fan2 segment 1 speed count ? index bah ......................................................................... 80 fan2 segment 2 speed count ? index bbh ......................................................................... 80 fan2 segment 3 speed count register ? index bch ........................................................... 81 fan2 segment 4 speed count register ? index bdh ........................................................... 81 fan2 segment 5 speed count register ? index beh ........................................................... 81 fan2 temperature mapping select ? index bfh ........................................................................... 81 c. fan3 index c0h- cfh ........................................................................................................ .... 82 vt3 boundary 1 temperature ? index c6h ........................................................................ 83 vt3 boundary 2 temperature ? index c7 .......................................................................... 83 vt3 boundary 3 temperature ? index c8h ........................................................................ 84 vt3 boundary 4 temperature ? index c9h ........................................................................ 84 fan3 segment 1 speed count ? index cah ......................................................................... 84 fan3 segment 2 speed count ? index cbh ......................................................................... 84 fan3 segment 3 speed count ? index cch .................................................................... 85 fan3 segment 4 speed count ? index cdh .................................................................... 85 fan3 segment 5 speed count ? index ceh ..................................................................... 85 fan3 temperature mapping select ? index cfh ........................................................................... 85 6.5 keyboard controller ....................................................................................................... ........ 86
F81867 dec, 2011 v0.12p commands ...................................................................................................................... ............... 87 ps/2 wakeup function .......................................................................................................... ........... 89 6.6 gpio ...................................................................................................................... ................ 89 6.6.1 gpio access method ..................................................................................... 89 6.6.2 gpiox st atus .................................................................................................. 91 6.7 watchdog timer function ................................................................................................... ... 94 6.8 acpi function ............................................................................................................. ........... 95 6.8.1power contro l........................................................................................................... 9 6 6.8.1.1wake up via sleep state ................................................................................................ .... 96 6.8.1.2wake up stage detection ................................................................................................ ... 96 6.8.1.3ac loss & resume control methods .................................................................................. 97 6.8.2intel power saving func tion deep sleep well (dsw ) ............................................. 98 6.8.3power saving controlle r (fintek erp mode) ......................................................... 100 6.8.4acpi ti ming ........................................................................................................... 10 4 6.8.4.1g3 to s0 ............................................................................................................................ 10 4 6.8.4.2g3 to s0 (only dsw) .................................................................................................... .... 105 6.8.4.3g3 to s0 (dsw & erp, ac resume green bold line) .................................................... 106 6.8.4.4dsw to s0 .............................................................................................................. .......... 107 6.8.4.5s0 to dsw .............................................................................................................. ........... 108 6.8.4.6s0 to g3? .............................................................................................................. ............. 109 6.9 uart ...................................................................................................................... ............. 110 6.10 amd tsi and intel peci 3.0 functions ................................................................................ 114 6.11 over voltage protection .................................................................................................. ..... 116 6.12 microcontroller ...................................................................................................................... 116 6.13 debug port function ...................................................................................................... ...... 116 6.14 h2e function ............................................................................................................. .......... 117 7. register de scription ................................................................................................... 119 7.1 global control registers .................................................................................................. .... 120 7.2 multifunction function register mapping table ................................................................... 128 7.2.1 multi function register mapping for fdc ................................................... 128 7.2.2 multi function register mapping for parallel port (lpt) ............................. 129 7.2.3 multi function register mappi ng for hardware monitor .............................. 129 7.2.4 multi function register mappi ng for kbc (ps/ 2 mouse) ............................. 130 7.2.5 multi function register mapping for gp io0x .............................................. 130 7.2.6 multi function register mapping for gp io1x .............................................. 130 7.2.7 multi function register mapping for gp io2x .............................................. 131 7.2.8 multi function register mapping for gp io3x .............................................. 131
F81867 dec, 2011 v0.12p 7.2.9 multi function register mapping for gp io4x .............................................. 132 7.2.10 multi function register mapping for gp io5x .............................................. 132 7.2.11 multi function register mapping for gp io6x .............................................. 132 7.2.12 multi function register mapping for gp io7x .............................................. 133 7.2.13 multi function register mapping for gp io8x .............................................. 133 7.2.14 multi function register mapping for wdt ................................................... 133 7.2.15 multi function register mapping for erp, led .......................................... 133 7.2.16 multi function register mapping for ir ....................................................... 134 7.2.17 multi function register mapping for i2c ..................................................... 134 7.2.18 multi function register mappi ng for uart 1 & uart 2 ............................. 135 7.2.19 multi function register mapping for ua rt 3 .............................................. 135 7.2.20 multi function register mapping for ua rt 4 .............................................. 135 7.2.21 multi function register mapping for ua rt 5 .............................................. 135 7.2.22 multi function register mapping for ua rt 6 .............................................. 136 7.3 fdc registers (cr00) ...................................................................................................... ... 136 7.4 parallel port registers (cr03) ............................................................................................ . 138 7.5 hardware monitor registers (cr04) .................................................................................... 140 7.6 kbc registers (cr05) ...................................................................................................... ... 140 7.7 gpio registers (cr06) ..................................................................................................... .. 142 7.8 gpio8x scan code registers ............................................................................................. 16 9 7.9 wdt registers (cr07) ...................................................................................................... .. 175 7.10 pme, acpi and eup registers (ldn 0x0a) ........................................................................ 176 7.11 rtc ram registers (ldn 0x0b) ......................................................................................... 187 7.12 h2e configuration registers (ldn 0x0e) ............................................................................ 187 7.13 debug port host side registers (ldn 0x0f) ....................................................................... 188 7.14 uart1 registers (cr10) ................................................................................................... .. 189 7.15 uart2 registers (cr11) ................................................................................................... .. 192 7.16 uart3 registers (cr12) ................................................................................................... .. 195 7.17 uart4 registers (cr13) ................................................................................................... .. 198 7.18 uart5 registers (cr14) ................................................................................................... .. 201 7.19 uart6 registers (cr15) ................................................................................................... .. 204 7.20 c side registers .............................................................................................................. .. 207 7.20.1 interrupt control c side register (base address 0x1000, 256 bytes) ........ 208 7.20.2 general control c side register (base addre ss 0x1100, 256 bytes) ......... 209 7.20.3 pwm control c side register (base addre ss 0x1200, 256 bytes) ............ 212 7.20.4 c side sram1 register (base a ddress 0x1300, 256 bytes) ..................... 214 7.20.5 c side sram2 register (base a ddress 0x1400, 256 bytes) ..................... 214
F81867 dec, 2011 v0.12p 7.20.6 host to ec control c side register (base address 0x1500, 256 bytes) .... 214 7.20.7 embedded flash control (base addr ess 0x1f00, 256 byte) ........................ 216 7.20.8 hardware monitor c side register (base address 0x2000, 256 byte) ........ 217 7.20.9 gpio c side register (base addre ss 0x2100, 256 by tes) ......................... 260 7.20.10 gpio8x scan code register s ...................................................................... 278 7.20.11 kbc c side register (base addre ss 0x2200, 256 by tes) .......................... 283 7.20.12 acpi c side register (base addre ss 0x2300, 256 bytes) ......................... 286 7.20.13 configuration register (base address 0x2400, 256 bytes) .......................... 289 7.20.14 ram c side register (base addre ss 0x2500, 8 by tes) .............................. 297 7.20.15 cir c side register (base addr ess 0x2600, 256 bytes) ........................... 298 7.20.16 debug port c side register (base addr ess 0x3200, 256 bytes)................ 299 8. electrical char acteristi cs ............................................................................................ 302 9. ordering in formation ................................................................................................... 305 10. top marking s pecificati on ........................................................................................... 305 11. package dimens ions .................................................................................................. 306 12. applicatio n circuit ....................................................................................................... 307
F81867 dec, 2011 v0.12p 10 1. general description the F81867 is the featured io chip with c based on 8-bit 8032 core & built in 8k*8 flash targeted for industrial pc system. equipped with one ieee 1284 parallel port, 6 uart ports with multi drop function (9-bit protocol), kbc, sir, acpi management function, portable cir with rc6 and one fdc. each uart provides 16/32/64/128 bytes fifo. the uart supports legacy speeds up to 115.2k bps as well as even higher baud rates of 230k, 460k, or 921k bps to support higher speed modems. the F81867 supports the enhanced parallel port (epp) and the extended capa bilities port (ecp). the F81867 supports keyboard and mouse interface which is 8042-based keyboard controller. the F81867 integrated with hardware monitor, 7 sets of voltage sensor, 3 sets of creative auto-controlling smart fans and 2 temperature sensor pins for the accurate dual current type temperature measurement for cpu thermal diode or ex ternal transistors 2n3906 and one local temperature. the F81867 provides flexible features for multi-directional application. for instance, supports 72 gpio pins, irq sharing function designed in uart feature for particular usage and accurate current mode h/w monitor will be worth in measurement of temperature. others, the F81867 supports newest intel peci 3.0 interfaces for new generational cpu temperature usage, intel ibx peak, i2c and amd tsi for temperature reading. in order to save the current consumption when the system is in the soft off state which is so called power saving function. the power saving function supports the system boot-on not only by pressing the power button but also by the wake-up events via gpio0x, gpio1x, ri1#, and ri2#. when the system enters the s3/s4/s5 state, F81867 can cut off the vsb power rail which supplies power source to the devices like the lan chip, the chipset, the sio, the audio codec, dram, and etc. the pc system can be emulated to g3-like state when the system enters s3/s4/s5 states. at the g3-like state, the F81867 consumes 5vsb power rail only. the integrated two control pins are utilized to turn on or off vsb power rail in the g3-like status. the turned on vsb rail is supplied to a wake up device to fulfill a low power consumption system which supports a wake up function. these features as above description will help you more and improve the product value. the F81867 is in the package of 128-lqfp. (14mm*14mm) 2. features general functions ? comply with lpc 1.1 ? support acpi 3.0 ? built in 8k*8 flash
F81867 dec, 2011 v0.12p 11 ? 8032 embedded microprocessor ? support wdt reset function ? support wdt wake up while erp function is enabled ? provide 4 sets of gpio (gpio0x/1x /5x/8x) smi event via pme# or sirq ? provide different sirq channels for gpio0x/1x/5x/8x ? support portable remote control via cir rc6 ? provide one fdc, kbc and parallel port ? provide 6 fully functional uart and 1 sir 9 programmable 16/32/64/128 bytes fifo 9 multi drop function & 128 bytes for uarts 9 support irq sharing function. 9 provide auto flow control function ? h/w monitor functions 9 support ovp & uvp for 3vcc and vin2&3 9 support smart fan fqst for fan 1 9 support peci 3.0 9 support ibx pch temperature reading via i2c 9 support amd tsi ? 72 gpio pins for flexible application ? provide 16 bytes serial id ? support led blinking function ? provide power saving function (comply erp lot 6.0) ? support intel deep sleep well (dsw) timing sequence ? provide wake-up events via power button, gpio0x, gpio1x, ri1#, and ri2# ? provide atx emulates at function ? 14.318/24/48 mhz clock input ? packaged in 128-lqfp fdc ? compatible with ibm pc at disk drive systems ? variable write pre-compensation with track selectable capability ? support vertical recording format ? dma enable logic ? 16-byte data fifos ? support floppy disk drives and tape drives ? detects all overrun and under run conditions ? built-in address mark detection circuit to simplify the read electronics ? completely compatible with industry standard 82077 ? 360k/720k/1.2m/1.44m/2.88m format; 250k, 300k, 500k, 1m, 2m bps data transfer rate
F81867 dec, 2011 v0.12p 12 parallel port ? one ps/2 compatible bi-directional parallel port ? support enhanced parallel port (epp) ? compatible with ieee 1284 ? support extended capabilities port (ecp) ? compatible with ieee 1284 ? enhanced printer port back-drive current protection hardware monitor functions ? 2 dual current type ( 3 o c) thermal inputs for cpu thermal diode and 2n3906 transistors ? provide one local temperature ? support temperature monitoring via thermistor ? temperature range: -60 o c~127 o c ? 8 sets voltage monitoring (4 external and 4 internal powers) ? high limit signal (pme#) for vcore ? 3 fan speed monitoring inputs ? 3 fan speed pwm/dc control outputs ? fanctrl 1~3 provides 4 frequency (23.5/11.75/5.875khz, & 200hz) select via the registers ? issue pme# and ovt# hardware signals output ? case intrusion detection circuit support peci 3.0 i2c interface ? support slave interface to report the hardware monitor data ? support master interface to get the thermal data via pch & mxm module support amd tsi interface keyboard controller ? compatibility with the 8042 ? support ps/2 mouse ? hardware gate a20 and hardware keyboard reset ? support kb, mouse wake up and swap function gpio function ? total 72 pins gpio ? interrupt status (wake up) support via gpio0x and gpio1x ? support different sirq channels via gpio0x, gpio1x, gpio5x and gpio8x
F81867 dec, 2011 v0.12p 13 ? all gpio supports digit io for input/output control, output data control, input status. ? support high/low level/pulse, open drain/push pull function selection ? all gpio could be accessed via 3 ways: configuration register port (4e/2e), index/data port and directly access to gpio only (digital i/o). please refer to the related register for detail. watch dog timer ? time resolution minute/second by option ? maximum 256 minutes or 256 seconds ? output signal via wdtrst#/pwrok ? wdt could also wake up via pme#, pswout# power saving function ? g3-like timing control ? comply with erp lot 6.0 ? built in soft start function for two control pins with vsb power sources control. ? event in via gpio0x, gpio1x, ri1#, and ri2# support intel cougar point timing (dsw) uart ? provide 6 fully functional uart ? 6 high-speed 16c550/16c650/16c750/16c850 compatible uarts ? provide auto flow control function ? baud rate supports 115.2k, max. up to 1.5m ? support irq 3,4,5,6,7,8,9,10,11 sharing ? provide multi drop (9-bits) function for gaming machine ? support irda version 1.0 sir protocol (multi with uart 6) ? support ring-in wake up via ri1# and ri2# infrared ? support irda version 1.0 sir protocol with maximum baud rate up to 115.2k bps (multi with uart 6) provide atx emulates at function provide serial id function ? provide 16 bytes for fixed fintek serial id
F81867 dec, 2011 v0.12p 14 ? provide 16 bytes for customer serial id ? use serial id tool (dos & window) to update the customer serial id provide scan code function (kb emulation key code) ? support scan code via gpio81~gpio87 ? windows os can detect the system volume control signal without any driver installation. ? support standard kb set 1 commands (except ?pause? key) ? see register for the detail setting cir ? provide simple functions such as up/down/left/right/enter/power on/power off ? provide simple/portable rc6 remote control commands ? the commands are based on the standard set 1 (except ?pause? key) 8 bit 8032 ? built in 8k*8 bits flash ? could access gpio, pwm, hardware monitor, kbc, acpi & cir functions package ? 128-pin lqfp (14mm * 14mm) green package noted: patented tw207103 tw207104 tw220442 us6788131 b1 twi235231 tw237183 twi263778
F81867 dec, 2011 v0.12p 15 3. block diagram cpu chipset usb sata floppy portable cir parallel uart gpio temperature voltage fan F81867 usio acpi ac?97 kbc peci 3.0 power saving ibx pch amd tsi scan code serial id
F81867 dec, 2011 v0.12p 16 4. pin configuration
F81867 dec, 2011 v0.12p 17 5. pin description 5.1 power pin pin pin name type description 31, 119 3vcc p power supply voltage input with 3.3v. 60 i_vsb3v p 3.3v internal standby po wer regulates from 5vsb for internal circuit usage. strongly recommend to place 0.1uf for the compensation. 84 vbat p battery voltage. place 1000pf for monitoring. 73 5vsb (v5a) p 5v standby power supply. 97 3vsb p analog power with 3.3v standby. 88 agnd p analog gnd. 22, 128 gnd p digital gnd. i/o 16st i lv /o d8 , s1v - ttl level bi-directional pin with schmitt trigger, 16ma source/sink capability. - low level bi-directional pin. outupt with 8 ma drive and 1ma sink capability. i/ood 12st, 5v i/ood 14st,5v i/ood 8st,5v i/od 16st , 5v - ttl level bi-directional pin, output can be selected to open drian or push pull by the register, with 12 ma source/sin k capability, 5v tolerance. - ttl level bi-directional pin with schmitt trigger, output can be selected to open drian or push pull by the register, with 14 ma so urce/sink capability, 5v tolerance. - ttl level bi-directional pin, output can be se lected to open drian or push pull by register, with 8 ma source/sink capability, 5v tolerance. - ttl level bi-directional pin with schmitt trigger, open drain output with 16 ma sink capability, 5v tolerance. od 16,u10 i/o 12st , 5v - open drain output pin with 16 ma sink capability, pull-up 10k
F81867 dec, 2011 v0.12p 18 5.2 clock pin pin name type pwr description 32 pciclk in st 3vcc 33mhz pci clock input. 33 clkin in st 3vcc system clock input. according to the input frequency 14.318/24/48mhz (default 48mhz). 5.3 lpc interface pin pin name type pwr description 23 lreset# in st 3vcc reset signal. it can connect to pcirst# signal on the host. 24 ldrq# o 16 3vcc encoded dma request signal. 25 serirq i/o 16st 3vcc serial irq input/output. 26 lframe# in st 3vcc indicates start of a new cycle or termination of a broken cycle. 27-30 lad[0:3] i/o 16st 3vcc these signal lines communicate address, control, and data information over the lpc bus between a host and a peripheral. 32 pciclk in st 3vcc 33mhz pci clock input. 33 clkin in st 3vcc system clock input. according to the input frequency 14.318/24/48mhz (default 48mhz). 5.4 fdc pin no. pin name type pwr description 9 gpio50 i/ood 14st, 5v 3vcc general purpose io. densel# od 14,5v drive density select. set to 1 ? high data rate.(500kbps, 1mbps) set to 0 ? low data rate. (250kbps, 300kbps) rts6# o 14 uart request to send. an active low signal informs the modem or data set that the controller is ready to send data. 10 gpio51 i/ood 14st, 5v 3vcc general purpose io. moa# od 14,5v motor a on. when set to 0, this pin enables disk drive 0. this is an open drain output. sin6 in st,5v uart serial input. used to receive serial data through the communication link. 11 gpio52 i/ood 14st, 5v 3vcc general purpose io. drva# od 14,5v drive select a. when set to 0, this pin enables disk drive a. this is an open drain output. sout6 o 14 uart serial output. used to transmit serial data out to the communication link. 12 gpio53 i/ood 14st, 5v 3vcc general purpose io. wdata# od 14,5v write data. this logic low open drain writes pre-compensation serial data to the selected fdd.
F81867 dec, 2011 v0.12p 19 an open drain output. dcd6# in st,5v data carrier detect. an active low signal indicates the modem or data set has detected a data carrier. 13 gpio54 i/ood 14st, 5v 3vcc general purpose io. dir# od 14,5v direction of the head step motor. an open drain output. logic 1 = outward motion logic 0 = inward motion ri6# in st,5v ring indicator. an active low signal indicates that a ring signal is being received from the modem or data set. 14 gpio55 i/ood 14st, 5v 3vcc general purpose io. step# od 14,5v step output pulses. this active low open drain output produces a pulse to move the head to another track. cts6# in st,5v clear to send is the modem control input. 15 gpio56 i/ood 14st, 5v 3vcc general purpose io. hdsel# od 14,5v head select. this open drain output determines which disk drive head is active. logic 1 = side 0 logic 0 = side 1 dtr6# o 14 uart data terminal ready. an active low signal informs the modem or data set that controller is ready to communicate. 16 gpio57 i/ood 14st, 5v 3vcc general purpose io. wgate# od 14,5v write enable. an open drain output. dsr6# in st,5v data set ready. an active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the uart. 17 gpio60 i/ood 12st, 5v 3vcc general purpose io. rdata# in st,5v the read data input signal from the fdd. dcd5# in st,5v data carrier detect. an active low signal indicates the modem or data set has detected a data carrier. pwm 0 ood 14st, 5v pwm0 output where its frequency range is 183hz~46.875khz. it can support various applications such as manual fan control, and backlight brightness control. 18 gpio61 i/ood 12st, 5v 3vcc general purpose io. trk0# in st,5v track 0. this schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. ri5# in st,5v ring indicator. an active low signal indicates that a ring signal is being received from the modem or data set. pwm 1 ood 12 pwm1 output where its frequency range is 183hz~46.875khz. it can support various applications such as manual fan control, and
F81867 dec, 2011 v0.12p 20 backlight brightness control. 19 gpio62 i/ood 12st, 5v 3vcc general purpose io. index# in st,5v this schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. cts5# in st,5v clear to send is the modem control input. pwm 2 ood 12 pwm2 output where its frequency range is 183hz~46.875khz. it can support various applications such as manual fan control, and backlight brightness control. 20 gpio63 i/ood 12st, 5v 3vcc general purpose io. wpt# in st,5v write protected. this active low schmitt input from the disk drive indicates that the diskette is write-protected. dtr5# o 12 uart data terminal ready. an active low signal informs the modem or data set that controller is ready to communicate. pwm 3 ood 12 pwm3 output where its frequency range is 183hz~46.875khz. it can support various applications such as manual fan control, and backlight brightness control. 21 gpio64 i/ood 12st, 5v 3vcc general purpose io. dskchg# in st,5v diskette change. this signal is active low at power on and whenever the diskette is removed. dsr5# in st,5v data set ready. an active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the uart. 5.5 parallel port (lpt port) pin no. pin name type pwr description 102 fanin3 in st,5v 3vcc fan 3 tachometer input. slct in st,5v an active high input on this pin indicates that the printer is selected. refer to the description of the parallel port for definition of this pin in ecp and epp mode. 103 gpio70 i/ood 12st, 5v 3vcc general purpose io. pe in st,5v an active high input on this pin indicates that the printer has detected the end of the paper. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. fanctl3 ood 12,5v aout fan 3 control output. this pin provides pwm duty-cycle output or a dac voltage output. pwm _dac3 in st,5v power on strapping pin: 1: pwm mode. 0: default is dac mode for fanctl3 (internal pull
F81867 dec, 2011 v0.12p 21 down 100k
F81867 dec, 2011 v0.12p 22 110 gpio77 i /ood 12st, 5v 3vcc general purpose io. stb# i/ood 12st,5v an active low output is used to latch the parallel data into the printer. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. pwm3 ood 12st, 5v pwm3 output where its frequency range is 183hz~46.875khz. it can support various applications such as manual fan control, and backlight brightness control. 111 gpio80 i/ood 12st, 5 v 3vcc general purpose io. support scan code function. pd0 i/o 12st,5v parallel port data bus bit 0. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 112 gpio81 i/ood 12st, 5v 3vcc general purpose io. support scan code function. pd1 i/o 12st,5v parallel port data bus bit 1. 113 gpio82 i/ood 12st, 5v 3vcc general purpose io. support scan code function. pd2 i/o 12st,5v parallel port data bus bit 2. 114 gpio83 i/ood 12st, 5v 3vcc general purpose io. support scan code function. pd3 i/o 12st,5v parallel port data bus bit 3. 115 gpio84 i/ood 12st, 5v 3vcc general purpose io. support scan code function. pd4 i/o 12st,5v parallel port data bus bit 4. 116 gpio85 i/ood 12st, 5v 3vcc general purpose io. support scan code function. pd5 i/o 12st,5v parallel port data bus bit 5. 117 gpio86 i/ood 12st, 5v 3vcc general purpose io. support scan code function. pd6 i/o 12st,5v parallel port data bus bit 6. 118 gpio87 i/ood 12st, 5v 3vcc general purpose io. support scan code function. pd7 i/o 12st,5v parallel port data bus bit 7. 5.6 hardware monitor pin pin name type pwr description 71 beep od 24t,5v i_vsb3v beep pin. gpio16 i/ood 12st,5v general purpose io. sda i lv /od 12st,5v i2c interface data pin. amd tsi & intel pch (ibx peak) data pin. cirrx# in st,5v cir receiver input. 72 peci i lv /o d8, s1 i_vsb3v peci interface pin. gpio17 i/ood 12st,5v general purpose io. 75 ovt# od 12,5v i_vsb3v over temperature signal output. 76 alert# od 12,5v i_vsb3v alert a signal when temperature over limit setting. gpio20 i/ood 24st,5v general purpose io. scl i lv /od 24st,5v i2c interface clock. cl ock output for amd tsi & intel pch (ibx peak). cirrx# in st,5v cir receiver input. 85 copen# in st,5v vbat case open detection #. this pin is connected to
F81867 dec, 2011 v0.12p 23 a specially designed low power cmos flip-flop backed by the battery for case open state preservation during power loss. 89 d- ain 3vsb analog gnd for thermal diode/transistor temperature. 90 d2+ ain 3vsb thermal diode/transistor temperature sensor input. 91 d1+(cpu) ain 3vsb cpu thermal diode/transistor temperature sensor input. this pin is for cpu use. 92 vref aout 3vsb voltage reference output. 93 vin4 ain 3vsb voltage input 4. 94 vin3 ain 3vsb voltage input 3. support ovp & uvp function, and default is disable alarm mode. 95 vin2 ain 3vsb voltage input 2. support ovp & uvp function, and default is disable alarm mode. 96 vin1 (vcore) ain 3vsb voltage input for vcore. 98 fanin1 in st,5v 3vcc fan 1 tachometer input. 99 fanctl1 ood 12,5v aout 3vcc fan 1 control output. this pin provides pwm duty-cycle output or a dac voltage output (internal pull down 100k , default). pwm _dac1 in st,5v power on strapping pin: 1: pwm mode. 0: default is dac mode for fanctl1 (internal pull down 100k , default). pwm _dac2 in st,5v power on strapping pin: 1: pwm mode. 0: default is dac mode for fanctl2 (internal pull down 100k 5.7 kbc function pin no. pin name type pwr description 34 kbrst# od 16,u10 3vcc keyboard reset. this pin is high after system reset. internal pull high 3.3v with 10k . 35 ga20 od 16,u10 3vcc gate a20 output. this pin is high after system reset. internal pull high 3.3v with 10k . 63 kdata i/od 16st,5v i_vsb3v ps/2 keyboard data. 64 kclk i/od 16st,5v i_vsb3v ps/2 keyboard clock. 61 mdata i/od 16st,5v i_vsb3v ps/2 mouse data. scl i lv /od 16st, 5v i2c interface clock pin. clock output for amd tsi & intel pch (ibx peak). 62 mclk i/od 16st,5v i_vsb3v ps/2 mouse clock.
F81867 dec, 2011 v0.12p 24 sda i lv /od 16st, 5v i2c interface data pin. amd tsi & intel pch (ibx peak) data pin. 5.8 acpi, erp pin pin name type pwr description 52 erp_ctrl0# od 12,5v i_vsb3v standby power rail control pin 0. this pin controls an external pmos to turn on or off the standby power rail. in the s5 state, the default is set to 1 to cut off the standby power rail. gpio00 i/ood 12st,5v general purpose io. 53 erp_ctrl1# od 12,5v i_vsb3v standby power rail control pin 1. this pin controls an external pmos to turn on or off the standby power rail. in the s5 state, the default is set to 1 to cut off the standby power rail. gpio01 i/ood 12st,5v general purpose io. 54 sus_warn# in st i_vsb3v this pin asserts low when the pch is planning to enter the dsw power state. it can detect 5vdual level with delay setting supported. the delay time is 1ms~8s (default 4s) gpio02 i/ood 12st,5v general purpose io. 55 sus_ack# od 12,5v i_vsb3v this pin must wait suswarn# signal for entering dsw power state. gpio03 i/ood 12st,5v general purpose io. 56 slp_sus# in st,lv i_vsb3v this pin asserts low which comes from pch to shut off suspend power rails externally to enhance power saving function. gpio04 i/ood 12st,5v general purpose io. 57 gpio05 i/ood 12st,5v i_vsb3v general purpose io. sout5 o 12 uart serial output. used to transmit serial data out to the communication link. 58 gpio06 i/ood 12st,5v i_vsb3v general purpose io. sin5 in t,5v uart serial input. used to receive serial data through the communication link. 59 gpio07 i/ood 12st,5v i_vsb3v general purpose io. rts5# o 12 uart request to send. an active low signal informs the modem or data set that the controller is ready to send data. 65 gpio10 i/ood 12st,5v i_vsb3v general purpose io. led_vsb ood 12,5v power led for vsb. 66 gpio11 i/ood 12st,5v i_vsb3v general purpose io. led_vcc ood 12,5v power led for vcc. 67 scl i lv /od 12st, 5v i_vsb3v i2c interface clock pin. clock output for amd tsi & intel pch (ibx peak).
F81867 dec, 2011 v0.12p 25 gpio12 i/ood 12st,5v general purpose io. irtx o 12 infrared transmitter output. uart 6 can?t be used if this function is valid. 68 sda i lv /od 12st, 5v i_vsb3v i2c interface data pin. amd tsi & intel pch (ibx peak) data pin. gpio13 i/ood 12st,5v general purpose io. irrx in st,5v infrared receiver input. uart 6 can?t be used if this function is valid. 69 gpio14 i/ood 12st,5v i_vsb3v general purpose io. atx_at_trap in t,5v power on trapping: atx emulates at function 1: atx mode (default, internal pull high 47k
F81867 dec, 2011 v0.12p 26 5.9 uart, sir pin pin name type pwr description 1 dcd2# in st,5v 3vcc data carrier detect. an active low signal indicates th e modem or data set has detected a data carrier. 2 ri2# in st,5v i_vsb3v ring indicator. an active low signal indicates that a ring signal is being received from the modem or dat a set. support wake up function. 3 cts2# in st,5v 3vcc clear to send is the modem control input. 4 dtr2# o 8 3vcc uart data terminal ready. an active low signa l informs the modem or data set that controller is read y to communicate. ovp_mode in t,u47, 5v power on strapping pin for over voltage protection (ovp). 1: default is disabled; internal pull high 47k
F81867 dec, 2011 v0.12p 27 40 rts3# o 8 3vcc uart request to send. an active low signal inform s the modem or data set that the controller is ready t o send data. gpio34 i/ood 8st, 5v general purpose io. 41 dsr3# in st,5v 3vcc data set ready. an active low signal indicates th e modem or data set is ready to establish a communication link and transfer data to the uart. gpio35 i/ood 8st, 5v general purpose io. 42 sout3 o 8 3vcc uart serial output. used to transmit serial data ou t to the communication link. gpio36 i/ood 8st, 5v general purpose io. 43 sin3 in st,5v 3vcc uart serial input. used to receive serial dat a through the communication link. gpio37 i/ood 8st, 5v general purpose io. 44 dcd4# in st,5v 3vcc data carrier detect. an active low signal indicates th e modem or data set has detected a data carrier. gpio40 i/ood 8st, 5v general purpose io. 45 ri4# in st,5v 3vcc ring indicator. an active low signal indicates that a ring signal is being received from the modem or dat a set. gpio41 i/ood 8st, 5v general purpose io. 46 cts4# in st,5v 3vcc clear to send is the modem control input. gpio42 i/ood 8st, 5v general purpose io. 47 dtr4# o 8 3vcc uart data terminal ready. an active low signa l informs the modem or data set that controller is read y to communicate. gpio43 i/ood 8st, 5v general purpose io. 48 rts4# o 8 3vcc uart request to send. an active low signal inform s the modem or data set that the controller is ready t o send data. gpio44 i/ood 8st, 5v general purpose io. 49 dsr4# in st,5v 3vcc data set ready. an active low signal indicates th e modem or data set is ready to establish a communication link and transfer data to the uart. gpio45 i/ood 8st, 5v general purpose io. 50 sout4 o 8 3vcc uart serial output. used to transmit serial data ou t to the communication link. gpio46 i/ood 8st, 5v general purpose io. 51 sin4 in st,5v 3vcc uart serial input. used to receive serial dat a through the communication link. gpio47 i/ood 8st, 5v general purpose io. 120 dcd1# in st,5v 3vcc data carrier detect. an active low signal indicates th e modem or data set has detected a data carrier. 121 ri1# in st,5v i_vsb3v ring indicator. an active low signal indicates that a ring signal is being received from the modem or dat a
F81867 dec, 2011 v0.12p 28 set. support wake up function. 122 cts1# in st,5v 3vcc clear to send is the modem control input. 123 dtr1# o 8 3vcc uart data terminal ready. an active low signa l informs the modem or data set that controller is read y to communicate. fan_40_100 in t,u47, 5v 3vcc power on strapping pin: 1(default): (internal pull high 47k ) power on fan speed default duty is 40%.(pwm) 0: (external pull down) power on fan speed default duty is 100%.(pwm) 124 rts1# o 8 3vcc uart request to send. an active low signal inform s the modem or data set that the controller is ready t o send data. config4e_2e in t,u47, 5v 3vcc power on strapping: 1(internal pull high 47k
F81867 dec, 2011 v0.12p 29 6. function description 6.1 power on strapping option the F81867 provides eight pins for power on hardwa re strapping to select required functions. see below table for the detail: pin no. symbol value description 4 ovp_mode 1 disable (default): internal pull high 47k . voltage protection function is enabled via setting the related registers. 0 enable ovp function. 69 atx_at_trap 1 atx mode (default, internal pull high 47k ). 0 at mode. 99 pwm_dac1 1 pwm mode. 0 dac mode (default, internal pull down 100k ) 101 pwm_dac2 1 pwm mode. 0 dac mode (default, internal pull down 100k ) 103 pwm_dac3 1 pwm mode. 0 dac mode (default, internal pull down 100k ) 123 fan40_100 1 power on fan speed default duty is 40%. ( default) 0 power on fan speed default duty is 100%. 124 config4e_2e 1 configuration register i/o port is 4e/4f. (default) 0 configuration register i/o port is 2e/2f. 126 i2c_addr 1 the i2c slave address is 0x5c (default) 0 the i2c slave address is 0x5a 6.2 fdc the floppy disk controller provides the interface be tween a host processor and one floppy disk drive. it integrates a controller and a digital data separator wi th write pre-compensation, data rate selection logic, microprocessor interface, and a set of registers. the fdc supports data transfer rates of 250 kbps, 300 kbps, 500 kbps, 1 mbps and 2 mbps. it operates in pc/at mode. the fdc configuration is handled by software and a set of configuration registers. status, data, and control registers facilitate the interface between t he host microprocessor and the disk drive, providing information about the condition and/or st ate of the fdc. these c onfiguration registers can select the data rate, enable interrupts, drives, and dma modes, and indicate errors in the data or oper ation of the fdc/fdd.
F81867 dec, 2011 v0.12p 30 6.3 parallel port the parallel port in F81867 supports an ibm xt/at compatible parallel port (spp), bi-directional parallel port ( bpp ), enhanced parallel port ( epp ), extended capabilities parallel port ( ecp ) mode. refer to the configuration registers for more informa tion on selecting the mode of operation. the below content is about the parallel port device re gister descriptions. all the registers are for software porting reference. parallel port data register ? base + 0 bit name r/w default description 7-0 data r/w 00h the output data to drive the parallel port data lines. ecp address fifo register ? base + 0 bit name r/w default description 7-0 ecp_afifo r/w 00h access only in ecp parallel port mode and the ecp_mode programmed in the extended control register is 011. the data written to this register is placed in the fifo and tagged as an address/rle. it is auto transmitted by the hardware. the operation is only defined for forward direction. it divide into two parts : bit 7 : 0: bits 6-0 are run length, indicating how many times the next byte to appear (0 = 1time, 1 = 2times, 2 = 3times and so on). 1: bits 6-0 are ecp address. bit 6-0 : address or rle depends on bit 7. device status register ? base + 1 bit name r/w default description 7 busy_n r - inverted version of parallel port signal busy. 6 ack_n r - version of parallel port signal ack#. 5 perror r - version of parallel port signal pe. 4 select r - version of parallel port signal slct. 3 err_n r - version of parallel port signal err#. 2-1 reserved r 11 reserved. return 11b when read. 0 tmout r - this bit is valid only in epp mode. return 1 when in other modes. it indicates that a 10us time out has occurred on the epp bus. 0: no time out error. 1: time out error occurred, write 1 to clear. device control register ? base + 2 bit name r/w default description 7-6 reserved - 11 reserved. return 11b when read.
F81867 dec, 2011 v0.12p 31 5 dir r/w 0 0: the parallel port is in output mode. 1: the parallel port is in input mode. it is auto reset to 1 when in spp mode. 4 ackirq_en r/w 0 enable an interr upt at the rising edge of ack#. 3 slin r/w 0 inverted and then drives the parallel port signal slin#. when read, the status of inverted slin# is return. 2 init_n r/w 0 drives the parallel port signal init#. when read, the status of init# is return. 1 afd r/w 0 inverted and then drives the parallel port signal afd#. when read, the status of inverted afd# is return. 0 stb r/w 0 inverted and then drives the parallel port signal stb#. when read, the status of inverted stb# is return. epp address register ? base + 3 bit name r/w default description 7-0 epp_addr r/w 00h write this register will cause the hardwar e to auto transmit the written data to the device with the epp address write protocol. read this register will cause the hardwar e to auto receive data from the device by with the epp address read protocol. epp data register ? base + 4 ? base + 7 bit name r/w default description 7-0 epp_data r/w 00h write this register will cause the hardwar e to auto transmit the written data to the device with the epp data write protocol. read this register will cause the hardwar e to auto receive data from the device by with the epp data read protocol. parallel port data fifo ? base + 400h bit name r/w default description 7-0 c_fifo r/w 00h data written to this fifo is auto trans mitted by the hardware to the device by using standard parallel port protocol. it is only valid in ecp and the ecp_mode is 010b.the operation is only for forward direction. ecp data fifo ? base + 400h bit name r/w default description 7-0 ecp_dfifo r/w 00h data written to this fifo when dir is 0 is auto transmitted by the hardware to the device by using ecp parallel port protocol. data is auto read from device into the fifo when dir is 1 by the hardware by using ecp parallel port protocol. read the fifo will return the content to the system. it is only valid in ecp and the ecp_mode is 011b.
F81867 dec, 2011 v0.12p 32 ecp test fifo ? base + 400h bit name r/w default description 7-0 t_fifo r/w 00h data may be read, written from system to the fifo in any direction. but no hardware handshake occurred on the parallel port lines. it could be used to test the empty, full and threshold of the fifo. it is only valid in ecp and the ecp_mode is 110b. ecp configuration register a ? base + 400h bit name r/w default description 7 irq_mode r 0 0: interrupt is isa pulse. 1: interrupt is isa level. only valid in ecp and ecp_mode is 111b. 6-4 impid r 001 000: the design is 16-bit implementation. 001: the design is 8-bit implementation (default). 010: the design is 32-bit implementation. 011-111: reserved. only valid in ecp and ecp_mode is 111b. 3 reserved - - reserved. 2 bytetran_n r 1 0: when transmitting there is 1 byte wait ing in the transceiver that does not affect the fifo full condition. 1: when transmitting the state of the full bit includes the byte being transmitted. only valid in ecp and ecp_mode is 111b. 1-0 reserved r 00 return 00 when read. only valid in ecp and ecp_mode is 111b. ecp configuration register b ? base + 401h bit name r/w default description 7 comp r 0 0: only send uncompressed data. 1: compress data before sending. only valid in ecp and ecp_mode is 111b. 6 reserved r 1 reserved. return 1 when read. only valid in ecp and ecp_mode is 111b. 5-3 ecp_irq_ch r 001 000: the interrupt selected with jumper. 001: select irq 7 (default). 010: select irq 9. 011: select irq 10. 100: select irq 11 101: select irq 14. 110: select irq 15. 111: select irq 5. only valid in ecp and ecp_mode is 111b. 2-0 ecp_dma_ch r 011 return the dma channel of ecp parallel port. only valid in ecp and ecp_mode is 111b.
F81867 dec, 2011 v0.12p 33 extended control register ? base + 402h bit name r/w default description 7-5 ecp_mode r/w 000 000: spp mode. 001: ps/2 parallel port mode. 010: parallel port data fifo mode. 011: ecp parallel port mode. 100: epp mode. 101: reserved. 110: test mode. 111: configuration mode. only valid in ecp. 4 errintr_en r/w 0 0: disable the interrupt generated on the falling edge of err#. 1: enable the interrupt generated on the falling edge of err#. 3 damen r/w 0 0: disable dma. 1: enable dma. dma starts when serviceintr is 0. 2 serviceintr r/w 1 0: enable the following case of interrupt. dmaen = 1: dma mode. dmaen = 0, dir = 0: set to 1 whenever there are writeintrthreshold or more bytes are free in the fifo. dmaen = 0, dir = 0: set to 1 whenever there are readintrthreshold or more bytes are valid to be read in the fifo. 1 fifofull r 0 0: the fifo has at least 1 free byte. 1: the fifo is completely full. 0 fifoempty r 0 0: the fifo contains at least 1 byte. 1: the fifo is completely empty. 6.4 hardware monitor 6.4.1 general description voltage for the 8-bit adc has the 8mv lsb, the maximu m input voltage of the analog pin is 2.048v. therefore the voltage under 2.048v (ex:1.5v) can be directly connect ed to these analog inputs. the voltage higher than 2.048v should be reduced by a factor with external resistors so as to obtain the input range. only 3vcc is an except ion for it is main power of the F81867. therefore 3vcc can directly connect to this chip?s power pin and need no external resistors. there are tw o functions in this pin with 3.3v. the first function is to supply internal analog power of the F81867 and the second function is that voltage with 3.3v is connected to internal serial resistors to monitor the +3.3v voltage. the internal serial resistors are two 150k
F81867 dec, 2011 v0.12p 34 2 1 2 v 12 r r r v vin + = + where v +12v is the analog input voltage, for example. if we choose r1=20k, r2=2k, the exact input vo ltage for v+12v will be 1.09v, which is within the tolerance. as for application circuit, it can be refer to the figure shown as follows. vin (< 2.04v) 8-bit adc with 8 mv lsb typical thermister connection r thm voltage inputs 10k, 25 c r vref 10k, 1% r 1 r2 (directly connect to the chip) 3vcc (directly connect to the chip) vin3.3 150k 150k 2n3906 typical bjt connection d+ d- vin (> 2.04v) fig 7-1 pme# interrupt for voltage is shown as figure 7-2. voltage exceeding or going below high limit will cause an interrupt if the prev ious interrupt has been reset by writing ?1? al l the interrupt status register. * voltage pme# mode * *interrupt reset when interrupt status registers are written 1 (p ulse mode ) fig 7-2 temperature sensor the F81867 monitors two remote temperature sensor s. these sensors can be measured from -60c to 127c for thermal diode & thermistor. more detail please refers to the register description. remote-sensor transistor manufacturers manufacturer model number panasonic 2sb0709 2n3906 philips pmbt3906
F81867 dec, 2011 v0.12p 35 (1) monitor temperature from ?thermistor? the F81867 can connect two thermistors to me asure environment temperature or remote temperature. the specification of t hermistor should be considered to (1) value is 3435k (2) resistor value is 10k at 25 c. in the figure 7-1, the thermistor is connected by a serial resistor with 10k , then connected to vref. (2) monitor temperature from ?thermal diode? also, if the cpu, gpu or external circ uits provide thermal diode for temperature measurement, the F81867 is capable to these sit uations. the build-in reference table is for pnp 2n3906 transistor. in the figure 7-1, the transisto r is directly connected into temperature pins. adc noise filtering the adc is integrating type with inherently good noise rejection. micro-power operation places constraints on high-frequency noise reje ction; therefore, careful pcb board layout and suitable external filtering are required for high -accuracy remote measurement in electronically noisy environment. high frequency emi is best filter ed at d+ and d- with an external 2200pf or 3300pf capacitor. too high capacitance may introduce errors due to the rise time of the switched current source. nearly all noise sources test ed cause the adc measurement to be higher than the actual temperature, dependi ng on the frequency and amplitude. over temperature signal (ovt#) ovt# alert for temperature is shown as fi gure 7-3. when monitored temperature exceeds the over-temperature threshold val ue, ovt# will be asserted until the temperature goes below the hysteresis temperature. t hyst tovt ovt# (level mode) ovt# (smi mode) fig 7-3 temperature pme# pme# interrupt for temperature is shown as fi gure 7-4. temperature exceeding high limit or going below hysteresis will cause an interrupt if t he previous interrupt has been reset by writing
F81867 dec, 2011 v0.12p 36 ?1? all the interrupt status register. *interrupt reset when interrupt status registers are written 1 pme# (pulse mode) * * t ovt t hhys * * t high t hhys fig 7-4 fan fan speed count inputs are provided by the signals from fans equipped with tachometer outputs. the level of these signals should be set to ttl level, and maximum input voltage cannot be over 5v. if the input signals from the tachometer output s are over the 5v, the external trimming circuit should be added to reduce the voltage to obtain the input specification. determine the fan counter according to: rpm 10 5 . 1 count 6 = in other words, the fan speed counter (12 bit resolution) has been read from register, the fan speed can be evaluated by the following equation. count 10 5 . 1 rpm 6 = as for fan, it would be best to use 2 pulses (4 phases fan) tachometer output per round. so the parameter ?count? under 5 bit filter is 4096~64 and rpm is 366~23438 based on the above equation. if using 8 phases fan, rpm would be from 183~11719. fan speed control the F81867 provides 2 fan speed control methods: 1. dac fan control 2. pwm duty cycle
F81867 dec, 2011 v0.12p 37 fanin monitor dc output voltage +12v r10k 1 2 3 jp1 con3 r 10k r 3.6k d1 1n4148 3 2 1 8 4 + - u1a lm358 r27k r 4.7k c 47u q1 pmos c 0.1u r 4.7k dac fan control the range of dc output is 0~vcc, controll ed by 8-bit register. 1 lsb is about 0.013v (vcc=3.3v). the output dc voltage is amplified by external op circuit, thus to reach maximum fan operation voltage, 12v. the output voltage will be given as followed: 256 value register 8bit programmed vcc (v) tage output_vol = and the suggested application circuit for linear fan control would be: fig 7-5 pwm duty fan control the duty cycle of pwm can be programmed by a 8- bit register. the default duty cycle is set to 100%, that is, the default 8-bit registers is set to ffh. the expression of duty can be represented as follows. % 100 255 value register 8bit programmed (%) duty_cycle = +12v fan r1 r2 nmos pnp transisto r c + - d s g fig 7-6
F81867 dec, 2011 v0.12p 38 fan speed control mechanism there are some modes to control fan speed and they are 1.manual mode, 2. auto mode (stage & linear). more detail, please refer to t he description of registers & below figure. fig 7-7 fan type & mode selection flow each fan can be controlled by 8 kinds of te mperature inputs: (1) t1 temperature (2) t2 temperature (3) t3 temperature (4) peci temperature (5) 4 suits i2c master temperature. fan 1 related register fan_prog_sel index 9fh [7] fan type select index 94 [1:0] fan mode select index 96 [1:0] fan count reading index a0h~a1h fan expect speed index a2h~a3h fan full speed count index a4h~a5h boundary index a6h~a9h segment speed index aah~aeh start step1: select fan_type (cr94) dac (linear) pwm manual mode auto mode step2 :select fan_mode cr96 [5:4] fan3 cr96 [3:2] fan2 cr96 [1:0] fan1 step3: set rpm fan1 :cr a2,a3 fan2 :cr b2,b3 fan3 :cr c2,c3 step3: set duty fan1 :cr,a3 fan2 :cr b3 fan3 :cr c3 rpm duty step4: set h/w monitor fan1 ? (boundary :cr a6~a9) (speed : cr aa ~ ae) fan2 ?(boundary :cr b6~b9) (speed : cr ba ~ be) fan3 ?(boundary :cr c6~c9) (speed : cr ca ~ ce) step3: set temp. follows fan1 :craf fan2 :crbf fan3 :crcf rpm duty step4: set h/w monitor fan1 ? (boundary :cr a6~a9) (speed : cr aa ~ ae) fan2 ?(boundary :cr b6~b9) (speed : cr ba ~ be) fan3 ?(boundary :cr c6~c9) (speed : cr ca ~ ce) step3: set temp. follows fan1 :craf fan2 :crbf fan3 :crcf start step1: select fan_type (cr94) dac (linear) pwm manual mode auto mode step2 :select fan_mode cr96 [5:4] fan3 cr96 [3:2] fan2 cr96 [1:0] fan1 step3: set rpm fan1 :cr a2,a3 fan2 :cr b2,b3 fan3 :cr c2,c3 step3: set duty fan1 :cr,a3 fan2 :cr b3 fan3 :cr c3 rpm duty step4: set h/w monitor fan1 ? (boundary :cr a6~a9) (speed : cr aa ~ ae) fan2 ?(boundary :cr b6~b9) (speed : cr ba ~ be) fan3 ?(boundary :cr c6~c9) (speed : cr ca ~ ce) step3: set temp. follows fan1 :craf fan2 :crbf fan3 :crcf rpm duty step4: set h/w monitor fan1 ? (boundary :cr a6~a9) (speed : cr aa ~ ae) fan2 ?(boundary :cr b6~b9) (speed : cr ba ~ be) fan3 ?(boundary :cr c6~c9) (speed : cr ca ~ ce) step3: set temp. follows fan1 :craf fan2 :crbf fan3 :crcf
F81867 dec, 2011 v0.12p 39 fan1 temperature mapping index afh fan 2 related register fan_prog_sel index 9fh [7] fan type select index 94 [3:2] fan mode select index 96 [3:2] fan count reading index b0h~b1h fan expect speed index b2h~b3h fan full speed count index b4h~b5h boundary index b6h~b9h segment speed index bah~beh fan1 temperature mapping index bfh fan 3 related register clk_tune_prog_en global control register : index 27h [0] multi function global control register : index 2bh [1:0] fan_prog_sel index 9fh [7] fan type select index 94 [5:4] fan mode select index 96 [5:4] fan count reading index c0h~c1h fan expect speed index c2h~c3h fan full speed count index c4h~c5h boundary index c6h~c9h segment speed index cah~ceh fan1 temperature mapping index cfh manual mode for manual mode, it generally acts as the software fan speed control. auto mode in auto mode, the F81867 provides the automatic fan speed control related to the temperature variation of cpu/gpu or the system. the F81867 can provide four temperature boundaries and five intervals, and each interval has its related fan speed count. all these values should be set by bios first. take fan1 for example, the 4 temperature bo undaries could be set from the register 0xa6 to 0xa9 and the five intervals for fan speed control could be set from register 0xaa to 0xae.the hysteresis setting (0 ~ 15c) could also be found in the register 0x98.
F81867 dec, 2011 v0.12p 40 there are two kinds for the auto modes they are the stage auto mode and the linear auto mode. the ?fan1_interpolation_en? in the register 0xafh is used for the linear auto mode enable. the following examples explain the differences for the stage auto mode and linear auto mode. stage auto mode in this mode, the fan keeps in a same speed fo r each temperature interval. and there are two types of fan speed setting: pwm duty and rpm %. a. stage auto mode (pwm duty) set the temperature limits as 70c, 60c, 50c, 40 c and the duty as 100%, 90%, 80%, 70%, 60% fig 7-8 stage mode fan control illustration a. once the temperature is under 40c, the lowest fan speed keeps in the 60% pwm duty. b. once the temperature is over 40c, 50cand 60 c, the fan speed will vary from 70%, 80% to 90% pwm duty and increasing with the temperature level. c. for the temperature higher than 70c, the fan speed keeps in 100% pwm duty. d. if set the hysteresis is 3c (default 4c), onc e the temperature becomes lower than 67c, the fan speed would reduce to 90% pwm duty. b. stage auto mode (rpm%) set the temperature as 70c, 60c, 50c, 40 c and the corresponding f an speed is 6,000 rpm, 5,400 rpm, 4,800 rpm, 4,200 rp m, and 3,600 rpm (assume the max fan speed is 6,000
F81867 dec, 2011 v0.12p 41 rpm). fig 7-9 stage mode fan control illustration a. once the temperature is lower than 40c, the lowest fan speed keeps in 3,600 rpm (60% of full speed). b. once the temperature is higher than 40c, 50c and 60c, the fan spe ed will vary from 4,200 rpm to 5,400 rpm and increasing with the temperature level. c. for the temperature higher than 70c, the fan speed keeps in the full speed 6,000 rpm. d. if the hysteresis is set as 3c (default 4c) , once temperature gets lower than 67c, the fan speed would reduce to 5,400 rpm. linear auto mode furthermore, F81867 also supports linear auto mo de. the fan speed would increase or decrease linearly with the temperature. there are also pwm duty and rpm% modes for it. a. linear auto mode (pwm duty i) set the temperature as 70c, 60c, 50c and 40c and the duty is 100%, 80%, 70%, 60% and 50%.
F81867 dec, 2011 v0.12p 42 fig 7-10 linear mode fan control illustration a. once the temperature is lower than 40c, the lowest fan speed keeps in the 50% pwm duty b. once the temperature becomes higher than 40c , 50c and 60c, the fan speed will vary from 50% to 80% pwm duty linearly with the temperat ure variation. the temp.-fan speed monitoring flash interval is 1sec. c. once the temperature goes over 70c, the fan speed will directly increase to 100% pwm duty (full speed). d. if set the hysteresis is 5c (default is 4c) , once the temperature becomes lower than 65c (instead of 70c), the fan speed will reduce from 100% pwm duty and decrease linearly with the temperature. b. linear auto mode (rpm%) set the temperature as 70c, 60c, 50c, 40 c and the corresponding f an speed is 6,000 rpm, 4,800 rpm, 4,200 rpm, 3,600 rpm and 3,000 rpm (a ssume the max fan speed is 6,000 rpm).
F81867 dec, 2011 v0.12p 43 fig 7-11 linear mode fan control illustration a. once the temperature is lower than 40c, the lowest fan speed keeps in 3,000 rpm (50% of full speed). b. once the temperature is over 40c,50c and 60 c, the fan speed will vary from 3,000 to 4,800 rpm almost linearly with the temperature vari ation because the temp.-fan speed monitoring flash interval is 1sec. c. once the temperature goes over 70c, the f an speed will directly increase to full speed 6,000 rpm. d. if the hysteresis is 5c (default is 4c), onc e the temperature becomes lower than 65c (instead of 70c), the fan speed wull reduce from full s peed and decrease linearly with the temperature. pwmout duty-cycle operating process in both ?manual rpm? and ?temperature rpm? modes, the F81867 adjust pwmout duty-cycle according to current fan count and expect ed fan count. it will operate as follows: 1. when expected count is 0x fff, pwmout duty-cycle will be set to 0x00 to turn off fan. 2. when expected count is 0x000, pwmout duty-cycl e will be set to 0xff to turn on fan with full speed. 3. if both (1) and (2) are not true, when pwmout duty-cycle decrease to min_duty( 00h), obviously the duty-cycle will decrease to 00h next, the F81867 will keep duty-cy cle at 00h for 1.6 seconds. after that,
F81867 dec, 2011 v0.12p 44 the F81867 starts to compare current fan count and expected count in order to increase or decrease its duty-cycle. this ensures that if there is any glitch during the period, the F81867 will ignore it. start duty stop duty fig 7-12 fan speed control with multi-temperature F81867 supports multi-temperature for fan 1 cont rol. fan 1 can be controlled up to 2 kinds of temperature inputs. this function works with linear auto mode which can extend to two linear slopes for fan 1 control. as below graph shows, this machine can support more silence fan control in low temperature and high fan speed in the high temperature segment. more detail setting please refers to the related registers. figure 7-13 support 2 linear application with multi-temp. setting in the figure below, tfan1 is the scaled temperatur e for fan1. t1 is the real temperature for the fan1 sensor. ta is another temperature data which can be used for linearly scale up or scale down the fan1 speed curve. tb would be the point which star ts the temperature scaling. the slope for the temperature curve over and under tb would be ctup and ctdn. 40% rpm/pwm % temperature 90% 100% 30 oc 80 oc 60% 50 oc s= pwm/ t =1 slope can be set
F81867 dec, 2011 v0.12p 45 1. ctup, ctdn can be programmed to 1, ?, ?, 0 2. ta can be selected to the same temp. source (ex:t1) tfan1= t1 + (ta-tb)*ctup ; tfan1= t1 + (ta-tb)*ctdn figure 7-14 in application, we can set the ta as the 2 nd sensor temperature and tb as the temperature which starts the scaling. so if the 2 nd sensor temperature ta is higher or lower than tb, the fan1 speed would be changed with it. ex: ta = t1, tb = 60, ctu = 1, ctd = 1/4 figure 7-15 fan_fault# fan_fault# will be asserted when the fan speed do esn?t meet the expected fan speed within a tb time temp. t1 ta tfan1 tfan1
F81867 dec, 2011 v0.12p 46 programmable period (default is 11 seconds) or when fan stops with respect to pwm duty-cycle which should be able to turn on the fan. there ar e two conditions may cause the fan_fault# event. (1). when pwm_duty reaches 0xff, the fan sp eed count can?t reach t he fan expected count on time. (figure 7-16) fan_fault# expected fan count 11 sec ( default ) current fan count duty-cycle 100% fig 7-16 (2). after the period of detecting fan full speed, when pwm_duty > min. duty, and fan count is still in 0xfff. 6.4.2 hardware moni tor device registers before the device registers, the following is a register map order which shows a summary of all registers. please refer to each register if you want more detail information. register cr01 ~ cr03 ? configuration registers register cr08 ~ cref ? peci/tsi/i2c control register register cr40 ~ cr8e ? peci 3.0 command and temperature setting register register cr10 ~ cr3a ? voltage setting register register cr90 ~ crcf ? fan control setting register ? fan1 detail setting cra0 ~ craf ? fan2 detail setting crb0 ~ crbf ? fan3 detail setting crc0 ~ crcf 6.4.2.1 configuration setting fan, voltage start up register ? index 01h bit name r/w reset default description 7-3 reserved 0h - 0 reserved 2 power_down r/w 5vsb 0 hardware monitor function power down function. 1 fan_start r/w 5vsb 1 1: enable startup of fan monitoring operations. 0: put the part in the standby mode. 0 v_t_start r/w 5vsb 1 1: enable startup of temperature and voltage monitoring operations 0: put the part in the standby mode.
F81867 dec, 2011 v0.12p 47 case open, alert, ovt mode register ? index 02h bit name r/w reset default description 7 reserved r/w - 0 dummy register. 6 case_beep_en r/w 5vsb 0 0: disable case open event output via beep. 1: enable case open event output via beep. 5-4 ovt_mode r/w 5vsb 0 00: the ovt# will be low active level mode. 01: the ovt# will be low pulse mode. 10: the ovt# will indicate by 1hz led function. 11: the ovt# will indicate by (400/800hz) beep output. 3 reserved r/w - 0 dummy register. 2 case_smi_en r / w 5vsb 0 0: disable case open event output via pme. 1: enable case open event output via pme. 1-0 alert_mode r/w 5vsb 0 00: the alert# will be low active level mode. 01: the alert# will be high active level mode. 10: the alert# will indicate by 1hz led function. 11: the alert# will indicate by (400/800hz) beep output. case open status register ? index 03h bit name r/w reset default description 7-1 reserved r/w - 0 reserved 0 case_sts r/w vbat 0 case open event status write 1 to cl ear if case open event cleared. (this bit is powered by vbat.) 6.4.2.2 peci/tsi/i2c setting tsi or ibex control register ? index 08h bit name r/w reset default description 7-1 tsi_addr r/w 5vsb 26h amd tsi or intel ibex slave address. 0 reserved - - - reserved i2c address control register ? index 09h bit name r/w reset default description 7 - 1 i 2 c _addr r / w 5vsb 0 i2c _ addr[7:1] is the slave address sent by the embedded master when using a block write command 0 reserved r/w - 0 reserved
F81867 dec, 2011 v0.12p 48 peci, tsi, ibex, beta register ? index 0ah bit name r/w reset defa ult description 7 beta_en2 r/w 5vsb 0 0: disable the t2 beta compensation. 1: enable the t2 beta compensation. 6 beta_en1 r/w 5vsb 0 0: disable the t1 beta compensation. 1: enable the t1 beta compensation. 5 intel_sel r/w 5vsb 1 this bit is used to select amd tsi or intel ibex when tsi_en is set to 1. 0: select amd 1: select intel 4 mxm_mode r/w lreset# 0 reserved 3-2 vtt_sel r/w 5vsb 0 peci (vtt) voltage selection. 00: vtt is 1.23v 01: vtt is 1.13v 10: vtt is 1.00v 11: vtt is 1.00v 1 tsi_en r/w 5vsb 0 set this bit 1 to enable amd tsi or intel ibex function 0 peci_en r/w lreset# 0 set this bit 1 to enable intel peci function cup socket select register ? index 0bh bit name r/w reset default description 7-4 cpu_sel r/w 5vsb 0 select the intel cpu socket number. 0000: no cpu presented. peci host will use ping () command to find the cpu address. 0001: cpu is in socket 0, i.e. peci address is 0x30. 0010: cpu is in socket 0, i.e. peci address is 0x31. 0100: cpu is in socket 0, i.e. peci address is 0x32. 1000: cpu is in socket 0, i.e. peci address is 0x33. others are reserved. 3-1 reserved - - 0 reserved. 0 domain1_en r/w 5vsb 0 if the cpu is selected as dual core. set this register 1 to read the temperature of domain1. tcc register ? index 0ch bit name r/w reset default description 7 - 0 tcc_temp r / w 5vsb 8?h55 tcc activation temperature. when peci is enabled, the absolute value of cpu temperature is calculated by the equation: cpu_temp = tcc_temp + peci reading. the range of this register is -128 ~ 127 o c.
F81867 dec, 2011 v0.12p 49 tsi offset register ? index 0dh bit name r/w reset default description 7 - 0 tsi_offset r / w 5vsb 0 this byte is used as the offset to be added to the cpu temperature reading of amd_tsi. the range of this register is -128 ~ 127 o c. configuration register ? index 0fh bit name r/w reset default description 7-2 reserved - - 0 reserved. 1-0 dig_rate_sel r/w 5vsb 0 reserved for fintek use only tsi temperature 0 ? index e0h bit name r/w reset default description 7-0 tsi_temp0 r / w 5vsb - this is the amd tsi reading if amd tsi enable. and will be highest temperature among cpu, mch and pch if intel temperature interface en able. the range is 0~255 o c. to access this byte, mch_bank_sel must set to ?0?. i2c_data0 r / w 5vsb 8?h00 this byte is used as multi-purpose: 1. the received data of receive protocol. 2. the first received byte of read word protocol. 3. the 10 th received byte of read block protocol. 4. the sent data for send byte pr otocol and write byte protocol. 5. the first send byte for write word protocol. 6. the first send byte for write block protocol. to access this byte, mch_bank _sel should be set to ?1?. tsi temperature 1 ? index e1h bit name r/w reset default description 7-0 tsi_temp1 r 5vsb - this is the high byte of intel te mperature interface pch reading. the range is 0~255 o c. to access this byte, mch_bank _sel should be set to ?0?. i2c_data1 r / w 5vsb 8?h00 this byte is used as multi-purpose: 1. the second received byte of read word protocol. 2. the 11 th received byte of read block protocol. 3. the second send byte for write word protocol. 4. the second send byte for write block protocol. to access this byte, mch_bank _sel should be set to ?1?.
F81867 dec, 2011 v0.12p 50 tsi temperature 2 low byte ? index e2h bit name r/w reset default description 7-0 tsi_temp2_lo r 5vsb - this is the low byte of intel tem perature interface cpu reading. the reading is the fraction part of cpu te mperature. bit 0 indicates the error status. 0: no error. 1: error code. to access this byte, mch_bank _sel should be set to ?0?. i2c_data2 r / w 5vsb 8?h00 this is the 12 th byte of the block read protocol. this byte is also used as the 3rd byte of block write protocol. to access this byte, mch_bank _sel should be set to ?1?. tsi temperature 2 high byte ? index e3h bit name r/w reset default description 7-0 tsi_temp2_hi r 5vsb - this is the high byte of intel te mperature interface cpu reading. the reading is the decimal part of cpu temperature. to access this byte, mch_bank _sel should be set to ?0?. i2c_data3 r / w 5vsb 8?h00 this is the 13 th byte of the block read protocol. this byte is also used as the 4th byte of block write protocol. to access this byte, mch_bank _sel should be set to ?1?. tsi temperature 3 ? index e4h bit name r/w reset default description 7-0 tsi_temp3 r 5vsb - this is the high byte of intel te mperature interface mch reading. the range is 0~255 o c. to access this byte, mch_bank _sel should be set to ?0?. i2c_data4 r / w 5vsb 8?h00 this is the 14 th byte of the block read protocol. this byte is also used as the 5th byte of block write protocol. to access this byte, mch_bank _sel should be set to ?1?. tsi temperature 4 ? index e5h bit name r/w reset default description 7 - 0 tsi_temp4 r 5vsb - this is the high byte of intel te mperature interface dimm0 reading. the range is 0~255 o c. to access this byte, mch_bank _sel should be set to ?0?.
F81867 dec, 2011 v0.12p 51 i2c_data5 r / w 5vsb 8?h00 this is the 15 th byte of the block read protocol. this byte is also used as the 6th byte of block write protocol. to access this byte, mch_bank _sel should be set to ?1?. tsi temperature 5 ? index e6h bit name r/w reset default description 7-0 tsi_temp5 r 5vsb - this is the high byte of intel te mperature interface dimm1 reading. the range is 0~255 o c. to access this byte, mch_bank _sel should be set to ?0?. i2c_data6 r / w 5vsb 8?h00 this is the 16 th byte of the block read protocol. this byte is also used as the 7th byte of block write protocol. to access this byte, mch_bank _sel should be set to ?1?. tsi temperature 6 ? index e7h bit name r/w reset default description 7-0 tsi_temp6 r 5vsb - this is the high byte of intel te mperature interface dimm2 reading. the range is 0~255 o c. to access this byte, mch_bank _sel should be set to ?0?. i2c_data7 r / w 5vsb 8?h00 this is the 17 th byte of the block read protocol. this byte is also used as the 8th byte of block write protocol. to access this byte, mch_bank _sel should be set to ?1?. tsi temperature 7 ? index e8h bit name r/w reset default description 7-0 tsi_temp7 r 5vsb - this is the high byte of intel te mperature interface dimm3 reading. the range is 0~255 o c. the above 9 bytes could also be used as the read data of block read protocol if the tsi is disable or pending. i2c_data8 r / w 5vsb 8?h00 this is the 18 th byte of the block read protocol. this byte is also used as the 9th byte of block write protocol. to access this byte, mch_bank _sel should be set to ?1?. i2c data buffer 9 ? index e9h bit name r/w reset default description 7-0 i2c_data9 r/w 5vsb ffh this is the 18 th byte of the block read protocol. this byte is also used as the 9th byte of block write protocol. to access this byte, mch_bank _sel should be set to ?1?.
F81867 dec, 2011 v0.12p 52 block write count register ? index ech bit name r/w reset default description 7 mch_bank_sel r / w 5vsb 0 this bit is used to select the register in index e0h to e9h. set ?0? to read the temperature bank and ?1? to access the data bank. 6 reserved - - 0 reserved 5 - 0 block_wr_cnt r / w 5vsb 0 use the register to specify the byte count of block write protocol. support up to 10 bytes. i2c command byte/tsi command byte ? index edh bit name r/w reset default description 7 - 0 i2c_cmd/tsi_cmd r / w 5vsb 0/1 there are actual two bytes for this index. tsi_cmd_prog select which byte to be programmed: 0: i2c_cmd, which is the command code for write byte/word, read byte/word, block write/read and process call protocol. 1: tsi_cmd, which is the command co de for intel temperature interface block read protocol and the data byte for amd tsi send byte protocol. i2c status ? index eeh bit name r/w reset default description 7 tsi_pending r / w lreset# 0 set 1 to pending auto tsi accessing. (in amd model, auto accessing will issue a send-byte followed a receive-by te; in intel model, auto accessing will issue a block read). to use the scl/ sda as i2c mast er, set this bit to ?1? first. 6 tsi_cmd_prog r / w 5vsb 0 set 1 to program tsi_cmd. 5 proc_kill r / w 5vsb 0 kill the current i2c transfer and return the state machine to idle. it will set a fail status if the current transfer is not completed. 4 fail_sts r 5vsb 0 this is set when proc_ki ll kill an un-completed transfer. it will be auto cleared by next i2c transfer. 3 i2c_ abt_err r 5vsb 0 this is the arbitration lost status if i2c command is issued. auto cleared by next i2c command. 2 i2c_ to_err r 5vsb 0 this is the timeout status if i2c comma nd is issued. auto cleared by next i2c command. 1 i2c__nac_err r 5vsb 0 this is the nack error status if i2c command is issued. auto cleared by next i2c command. 0 i2c__ready r 5vsb 1 0: i2c transfer is in process. 1: ready for next i2c command.
F81867 dec, 2011 v0.12p 53 i2c protocol select ? index efh bit name r/w reset default description 7 i2c_start w - 0 write ?1? to trigger i2c transfer with the protocol specified by i2c_protocol. 6 - 4 reserved - - - reserved. 3 - 0 i2c_ _protocol r / w 5vsb 0 select what protocol if i2c transfer is triggered. 0001b: send byte. 0010b: write byte. 0011b: write word. 0100b: reserved. 0101b: block write. 0111b: quick command (write). 1001b: receive byte. 1010b: read byte. 1011b: read word. 1101b: block read. 1111b: reserved otherwise: reserved. 6.4.2.3 peci 3.0 & temperature setting peci 3.0 command and register peci configuration register ? index 40h bit name r/w reset default description 7 rdiamsr_cmd_en r/w 5vsb 0 when peci temperature monitoring is enabled, set this bit 1 will generate a rdiamsr() command before a gettemp() command. 6 c3_update_en r/w 5vsb 0 if rdiamsr_cmd_en is not set to 1, the temperature data is not allowed to be updated when the completion code of rdiamsr() is 0x82. 5-4 reserved r - - reserved 3 c3_ptemp_en r/w 5vsb 0 set this bit 1 to enable updating positive value of temperature if the completion code of rdiamsr() is 0x82. 2 c0_ptemp_en r/w 5vsb 0 set this bit 1 to enable updating positive value of temperature if the completion code of rdiamsr() is not 0x82 and the bit 8 of completion code is not 1 either. 1 c3_all0_en r/w 5vsb 0 set this bit 1 to enable updating temperature value 0x0000 if the completion code of rdiamsr() is 0x82. 0 c0_all0_en r/w 5vsb 0 set this bit 1 to enable updating temperature value 0x0000 if the completion code of rdiamsr() is not 0x82 and the bit 8 of completion code is not 1 either. peci master control register ? index 41h bit name r/w reset default description 7 peci_cmd_start w 5vsb - write 1 to this bit to start a peci command when using as a peci master. (peci_pending must be set to 1)
F81867 dec, 2011 v0.12p 54 6-5 reserved r - - reserved 4 peci_pending r/w 5vsb 0 set this bit 1 to stop monitoring peci temperature. 3 reserved r - - reserved 2-0 peci_cmd r/w 5vsb 3?h0 peci command to be us ed by peci master. 000: ping() 001: getdib() 010: gettemp() 011: rdiamsr() 100: rdpkgconfig() 101: wrpkgconfig() others: reserved peci master status register ? index 42h bit name r/w reset default description 7-3 reserved r - - reserved 2 abort_fcs r/wc 5vsb - this bit is the abort fcs status of peci master commands. write this bit 1 or read this byte will clear this bit to 0. 1 peci_fcs_err r/wc 5vsb - this bit is the fcs error status of peci master commands. write this bit 1 or read this byte will clear this bit to 0. 0 peci_finish r/wc 5vsb - this bit is the command finish status of peci master commands. write this bit 1 or read this byte will clear this bit to 0. peci master data0 register ? index 43h bit name r/w reset default description 7-0 peci_data0 r/w 5vsb 0 for rdiamsr(), rdpkgconfig() and wrpkgconfig() command, this byte represents ?host id[7:1] & retry[0]?. please refer to peci interface specification for more detail. peci master data1 register ? index 44h bit name r/w reset default description 7-0 peci_data1 r/w 5vsb 0 for rdiamsr() , this byte represents ?processor id?. for rdpkgconfig() and wrpkgconfig() , this byte represents ?index?. please refer to peci interface specification for more detail. peci master data2 register ? index 45h bit name r/w reset default description 7-0 peci_data2 r/w 5vsb 0 for rdiamsr(), this byte is the leas t significant byte of ?msr address?. for rdpkgconfig() and wrpkgconfig(), this byte is the least significant byte of ?parameter?. please refer to peci interface specification for more detail.
F81867 dec, 2011 v0.12p 55 peci master data3 register ? index 46h bit name r/w reset default description 7-0 peci_data3 r/w 5vsb 0 for rdiamsr(), this byte is the most significant byte of ?msr address?. for rdpkgconfig() and wrpkgconfig(), this byte is the most significant byte of ?parameter?. please refer to peci interface specification for more detail. peci master data4 register ? index 47h bit name r/w reset default description 7-0 peci_data4 r/w 5vsb 0 for getdib() , this byte represents ?device info? for gettemp(), this byte represents the least significant byte of temperature. for rdiamsr() and rdpkgconfig() , this byte is ?completion code?. for wrpkgconfig(), this byte represents ?data[7:0]? peci master data5 register ? index 48h bit name r/w reset default description 7-0 peci_data5 r/w 5vsb 0 for getdib() , this byte represents ?revision number? for gettemp(), this byte represents the most significant byte of temperature. for rdiamsr() and rdpkgconfig() , this byte represents ?data[7:0]? for wrpkgconfig(), this byte represents ?data[15:8]? peci master data6 register ? index 49h bit name r/w reset default description 7-0 peci_data6 r/w 5vsb 0 for rdiamsr() and rdpkgconfig() , this byte represents ?data[15:8]?. for wrpkgconfig(), this byte represents ?data[23:16]? peci master data7 register ? index 4ah bit name r/w reset default description 7-0 peci_data7 r/w 5vsb 0 for rdiamsr() and rdpkgconfig() , this byte represents ?data[23:16]?. for wrpkgconfig(), this byte represents ?data[31:24]? peci master data8 register ? index 4bh bit name r/w reset default description 7-0 peci_data8 r/w 5vsb 0 for rdiamsr() and rdpkgconfig() , this byte represents ?data[31:24]?. for wrpkgconfig(), this byte represents ?aw fcs? peci master data9 register ? index 4ch bit name r/w reset default description 7-0 peci_data9 r/w 5vsb 0 for rdiamsr(), this byte represents ?data[39:32]?. for wrpkgconfig(), this byte represents ?completion code?
F81867 dec, 2011 v0.12p 56 peci master data10 register ? index 4dh bit name r/w reset default description 7-0 peci_data10 r/w 5vsb 0 for rdiamsr(), this byte represents ?data[47:40]?. peci master data11 register ? index 4eh bit name r/w reset default description 7-0 peci_data11 r/w 5vsb 0 for rdiamsr(), this byte represents ?data[55:48]?. peci master data12 register ? index 4fh bit name r/w reset default description 7-0 peci_data12 r/w 5vsb 0 for rdiamsr(), this byte represents ?data[63:56]?. hwm manual control register1 ? index 50h bit name r/w reset default description 7 load_ch w - - write 1 to load a temperature or voltage channel to be converted 6 stop_ch r/w 5vsb 0 set to 1 when load a channel will generate a one-shot conversion. 5 hold_ch r/w 5vsb 0 set to 1 when load a channel will keep converting this channel. 4:0 channel r/w 5vsb 0 first channel to be converted when load_ch is set to 1. 00000: vcc 00001: vin1 00010: vin2 00011: vin3 00100: vin4 00101: vsb3v 00110: vbat 00111: 5vsb 10000: intel peci 10001: t1 10010: t2 11000: amd tsi/intel ibex hwm manual control status register 1 ? index 51h bit name r/w reset default description 7 reserved - - - reserved 6 v_conv_sts r 5vsb - at least one of the voltage channels had finish converting. 5 peci_conv_sts wc 5vsb - peci channel had finish converting 4 tsi_conv_sts wc 5vsb - tsi channel had finish converting 3 reserved - - reserved 2 t2_conv_sts w c 5vsb - t2 channel had finish converting 1 t1_conv_sts w c 5vsb - t1 channel had finish converting 0 reserved - - reserved
F81867 dec, 2011 v0.12p 57 hwm manual control status register 2 ? index 52h bit name r/w reset default description 7 5vsb_conv_sts w c 5vsb - 5vsb voltage channel had finish converting 6 vbat_conv_sts wc 5vsb - vbat voltage channel had finish converting 5 vsb3v_conv_sts wc 5vsb - vsb3v voltage channel had finish converting 4 vin4_conv_sts wc 5vsb - vin4 voltage channel had finish converting 3 vin3_conv_sts wc 5vsb - vin3 voltage channel had finish converting 2 vin2_conv_sts wc 5vsb - vin2 voltage channel had finish converting 1 vin1_conv_sts wc 5vsb - vin1 voltage channel had finish converting 0 vcc_conv_sts w c 5vsb - vcc voltage channel had finish converting hwm raw data register 1 ? index 55h bit name r/w reset default description 7 - 0 raw_data_l r 5vsb 0 low byte of hm converting raw data hwm raw data register 2 ? index 56h bit name r/w reset default description 7 - 2 reserved - - - reserved 1 - 0 raw_data_h r 5vsb 0 the highest two bits of hm converting raw data temperature register temperature pme# enable register ? index 60h bit name r/w reset default description 7 reserved r/w - 0 reserved 6 en_ t2_ovt_pme r/w 5vsb 0 if set this bit to 1, pme# signal wi ll be issued when temp2 exceeds ovt setting. 5 en_ t1_ovt_pme r/w 5vsb 0 if set this bit to 1, pme# signal wi ll be issued when temp1 exceeds ovt setting. 4 en_ t0_ ovt_pme r/w 5vsb 0 if set this bit to 1, pme# signal will be issued when temp0 exceeds ovt setting. 3 reserved r/w - 0 reserved 2 en_ t2_exc_pme r/w 5vsb 0 if set this bit to 1, pme# signal will be issued when temp2 exceeds high limit setting. 1 en_ t1_exc_pme r/w 5vsb 0 if set this bit to 1, pme# signal will be issued when temp1 exceeds high limit setting. 0 en_ t0_exc_pme r/w 5vsb 0 if set this bit to 1, pme# signal will be issued when temp0 exceeds high limit setting.
F81867 dec, 2011 v0.12p 58 temperature interrupt status register ? index 61h bit name r/w reset default description 7 reserved r/w - 0 reserved 6 t2_ovt _sts r/w 3vcc 0 this bit gets 1 to indicate temp2 temperature sensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. write 1 to clear this bit, write 0 to ignore. 5 t1_ovt _sts r/w 3vcc 0 this bit gets 1 to indicate temp1 temperature sensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. write 1 to clear this bit, write 0 to ignore. 4 t0_ovt _sts r/w 3vcc 0 a one indicates temp0 temperature s ensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. write 1 to clear this bit, write 0 will be ignored. 3 reserved r/w - 0 reserved 2 t2_exc _sts r/w 3vcc 0 this bit gets 1 to indicate temp2 temperature sensor has exceeded high limit or below the ?high limit ?hysteresis? limit. write 1 to clear this bit, write 0 to ignore. 1 t1_exc _sts r/w 3vcc 0 this bit gets 1 to indicate temp1 temperature sensor has exceeded high limit or below the ?high limit ?hysteresis? limit. write 1 to clear this bit, write 0 to ignore. 0 t0_exc _sts r/w 3vcc 0 a one indicates temp0 temperature sens or has exceeded high limit or below the ?high limit ?hysteresis? limit. write 1 to clear this bit, write 0 will be ignored. temperature real time status register ? index 62h bit name r/w reset default description 7 reserved r/w - 0 reserved 6 t2_ovt r/w 3vcc 0 set when the temp2 exceeds the ovt limit. clear when the temp2 is below the ?ovt limit ?hysteresis? temperature. 5 t1_ovt r/w 3vcc 0 set when the temp1 exceeds the ovt limit. clear when the temp1 is below the ?ovt limit ?hysteresis? temperature. 4 t0_ovt r/w 3vcc 0 set when the temp0 exceeds the ovt limit. clear when the temp0 is below the ?ovt limit ?hysteresis? temperature. 3 reserved r/w - 0 reserved 2 t2_exc r/w 3vcc 0 set when the temp2 exceeds the high limit. clear when the temp2 is below the ?high limit ?hysteresis? temperature. 1 t1_exc r/w 3vcc 0 set when the temp1 exceeds the high limit. clear when the temp1 is below the ?high limit ?hysteresis? temperature. 0 t0_exc r/w 3vcc 0 set when the temp0 exceeds the high limit. clear when the temp0 is below the ?high limit ?hysteresis? temperature.
F81867 dec, 2011 v0.12p 59 temperature beep enable register ? index 63h bit name r/w reset default description 7 reserved r/w - 0 reserved 6 en_ t2_ ovt_beep r/w 5vsb 0 if set this bit to 1, beep signal will be issued when temp2 exceeds ovt limit setting. 5 en_ t1_ ovt_beep r/w 5vsb 0 if set this bit to 1, beep signal will be issued when temp1 exceeds ovt limit setting. 4 en_ t0_ ovt_beep r/w 5vsb 0 if set this bit to 1, beep signal will be issued when temp0 exceeds ovt limit setting. 3 reserved r/w - 0 reserved 2 en_ t2_exc_beep r/w 5vsb 0 if set this bit to 1, beep signal will be issued when temp2 exceeds high limit setting. 1 en_ t1_exc_beep r/w 5vsb 0 if set this bit to 1, beep signal will be issued when temp1 exceeds high limit setting. 0 en_ t0_exc_beep r/w 5vsb 0 if set this bit to 1, beep signal will be issued when temp0 exceeds high limit setting. t1 ovt and high limit temperature select register ? index 64h bit name r/w reset default description 7-6 reserved r/w - 0 reserved 5-4 ovt_temp_sel r/w 5vsb 0 select the source temperature for t1 ovt limit. 0: select t1 to be compared to temperature 1 ovt limit. 1: select cpu temperature from pec i to be compared to temperature 1 ovt limit. 2: select cpu temperature from amd tsi or intel pch i2c to be compared to temperature 1 ovt limit. 3: select the max temperature from intel pch i2c to be compared to temperature 1 ovt limit. 3-2 reserved r/w - 0 reserved 1-0 high_ temp_sel r/w 5vsb 0 select the source temperature for t1 high limit. 0: select t1 to be compared to temperature 1 high limit. 1: select cpu temperature from pec i to be compared to temperature 1 high limit. 2: select cpu temperature from amd tsi or intel pch i2c to be compared to temperature 1 high limit. 3: select the max temperature from intel pch i2c to be compared to temperature 1 high limit.
F81867 dec, 2011 v0.12p 60 ovt and alert output enable register 1 ? index 66h bit name r/w reset default description 7 reserved r/w - 0 reserved 6 en_t2_alert r/w 5vsb 0 enable temperature 2 alert event (a sserted when temperature over high limit) 5 en_t1_alert r/w 5vsb 0 enable temperature 1 alert event (a sserted when temperature over high limit) 4 en_t0_alert r/w 5vsb 0 enable temperature 0 alert event (asse rted when temperature over high limit) 3 reserved r/w - 0 reserved 2 en_t2_ovt r/w 5vsb 0 enable over temperature (ovt ) mechanism of temperature2. 1 en_t1_ovt r/w 5vsb 1 enable over temperature (ovt ) mechanism of temperature1. 0 en_t0_ovt r/w 5vsb 0 enable over temperature (ovt ) mechanism of temperature0. temperature sensor type register ? index 6bh bit name r/w reset default description 7-4 reserved ro - 0 reserved 3 reserved ro - 0 reserved 2 t2_mode r/w 5vsb 1 0: temp2 is connected to a thermistor. 1: temp2 is connected to a bjt. (default) 1 t1_mode r/w 5vsb 1 0: temp1 is connected to a thermistor 1: temp1 is connected to a bjt.(default) 0 reserved r - 0 reserved temp1 limit hystersis select register ? index 6ch bit name r/w reset default description 7-4 temp1_hys r/w 5vsb 4h limit hysteresis. (0~15 o c) temperature and below the (boundary ? hysteresis). 3-0 temp0_hys r/w 5vsb 4h limit hysteresis. (0~15 o c) temperature and below the (boundary ? hysteresis). temp2 and temp3 limit hyst ersis select register ? index 6dh bit name r/w reset default description 7-4 reserved r - 0 reserved 3-0 temp2_hys r/w 5vsb 4h limit hysteresis. (0~15 o c) temperature and below the ( boundary ? hysteresis ).
F81867 dec, 2011 v0.12p 61 diode open status register ? index 6fh bit name r/w reset default description 7-6 reserved r - - reserved 5 peci_open r 3vcc - when peci interface is enabled, ?1? indicates an error code (0x0080 or 0x0081) is received from peci slave. 4 tsi_open r 3vcc - when tsi interface is enabled, ?1? indicates the error of not receiving nack bit or a timeout occurred. 3 reserved r - - reserved 2 t2_diode_open r 3vcc - ?1? indicates external diode 2 is open or short 1 t1_diode_open r 3vcc - ?1? indicates external diode 1 is open or short 0 t0_diode_open ro 3vcc - this register indicates the abno rmality of temperature 0 measurement. temperature ? index 70h- 8dh address attribute reset default value description 70h ro 3vcc -- temperature 0 reading. the unit of reading is 1 o c.at the moment of reading this register. 71h reserved 3vcc ffh reserved 72h r 3vcc -- temperature 1 reading. t he unit of reading is 1 o c.at the moment of reading this register. 73h r 3vcc -- reserved 74h r 3vcc -- temperature 2 reading. t he unit of reading is 1 o c.at the moment of reading this register. 75-79h r 3vcc -- reserved 7ah r 3vcc -- the data of cpu temperature from digital interface after iir filter. (available if intel ibx or amd tsi interface is enabled) 7bh r 3vcc -- the raw data of pch temperature from digital interface. (only available if intel ibx interface is enabled) 7ch r 3vcc -- the raw data of mch read from digital interface. (only available if intel ibx interface is enabled) 7dh r 3vcc -- the raw data of maximum temperature between cpu/pch/mch from digital interface. (only ava ilable if intel ibex interface is enabled) 7eh r 3vcc -- the data of cpu temperature from digital interface after iir filter. (only available if peci interface is enabled) 80h r/w 5vsb 64h temperature sensor 0 ovt limit. the unit is 1 o c. 81h r/w 5vsb 55h temperature sensor 0 high limit. the unit is 1 o c. 82h r/w 5vsb 64h temperature sensor 1 ovt limit. the unit is 1 o c.
F81867 dec, 2011 v0.12p 62 83h r/w 5vsb 55h temperature sensor 1 high limit. the unit is 1 o c. 84h r/w 5vsb 64h temperature sensor 2 ovt limit. the unit is 1 o c. 85h r/w 5vsb 55h temperature sensor 2 high limit. the unit is 1 o c. 86-8bh r -- -- reserved 8c~8dh r -- ffh reserved t1 slope adjust register ? index 7fh bit name r/w reset default description 7-4 reserved - - - reserved 3 t1_add r/w 5vsb 0h this bit is the sign bit for t1 reading slope adjustment. see t1_scale below for detail. 2-0 t1_scale r/w - 0h t1_add t1_scale slope x 00 no adjustment 0 01 15/16 0 10 31/32 0 11 63/64 1 01 17/16 1 10 33/32 1 11 65/64 temperature filter select register ? index 8eh bit name r/w reset default description 7-6 iir-queur3 r/w 5vsb 2?b10 the queue time for second filter to quickly update values. 00: 8 times. 01: 12 times. 10: 16 times. (default) 11: 24 times. 5-4 iir-queur2 r/w 5vsb 2?b10 the queue time for second filter to quickly update values. 00: 8 times. 01: 12 times. 10: 16 times. (default) 11: 24 times. 3-2 iir-queur1 r/w 5vsb 2?b10 the queue time for second filter to quickly update values. 00: 8 timers. 01: 12 times. 10: 16 times. (default) 11: 24 times.
F81867 dec, 2011 v0.12p 63 1-0 iir-queur_dig r/w 5vsb 2?b10 the queue time for second filter to quickly update values. (for cpu temperature from peci or tsi interface) 00: 8 timers. 01: 12 times. 10: 16 times. (default) 11: 24 times. 6.4.2.4 voltage setting voltage-protect shut down enable register ? index 10h bit name r/w reset default description 7 reserved - - 0 reserved. 6 v3_vp_en r/w vbat* 0 voltage-protect shut down enable for vin3 5 v2_vp_en r/w vbat* 0 voltage-protect enable for vin2 4-1 reserved - - 0 reserved 0 vcc_vp_en r/w vbat* 0 voltage-protect shut down enable for 3vcc voltage-protect status register ? index 11h bit name r/w reset default description 7-6 reserved - - 0 reserved. 0 v_exc_vp r/wc vbat/ 5vsb* 0 this bit is voltage-protect status. once one of the monitored voltages (3vcc, vin2, vin3) over its related over-voltage limits or under its related under-voltage limits and if the related voltage-protect shut down enable bit is set, this bit will be set to 1. write a 1 to this bit will clear it to 0. (this bit is powered by vbat) * reset by vbat when ovp_mode is ?0?, reset by 5vsb when ovp_mode is ?1? voltage-protect configuration register ? index 12h bit name r/w reset default description 7-4 reserved - - - reserved.
F81867 dec, 2011 v0.12p 64 3-2 pu_time r/w vbat 2?h1 pson# de-active time select for voltage protection. 00: pson# tri-state 0.5 se c and then inverted of s3# when over voltage or under voltage occurred. 01: pson# tri-state 1 sec and then inve rted of s3# when over voltage or under voltage occurred. 10: pson# tri-state 2 sec and then inve rted of s3# when over voltage or under voltage occurred. 11: pson# tri-state 4 sec and then inve rted of s3# when over voltage or under voltage occurred. 1-0 vp_en_delay r/w vbat 2?h2 vp_en_delay could set the delay time to start voltage protecting after vdd power is ok when ovp_mode is 1. (ovp_mode is strapped by rts1# pin) 00: bypass 01: 50ms 10: 100ms 11: 200ms voltage1 pme# enable register ? index 14h bit name r/w reset default description 7-2 reserved - - 0 reserved 1 en_v1_pme r/w 5vsb 0 a one enables the corresponding interrupt status bit for pme# interrupt. set this bit 1 to enable pme# function for vin1. 0 reserved - - - reserved voltage1 interrupt status register ? index 15h bit name r/w reset default description 7-2 reserved -- - 0 reserved 1 v1_ exc _sts r/w 5vsb 0 this bit is set when the vin1 is over the high limit. write 1 to clear this bit, write 0 will be ignored. 0 reserved - - - reserved voltage1 exceeds real time status register 1 ? index 16h bit name r/w reset default description 7-2 reserved -- - 0 reserved 1 v1_exc ro 5vsb 0 a one indicates vin1 exceeds the high lim it. a zero indicates vin1 is in the safe region. 0 reserved -- - 0 reserved
F81867 dec, 2011 v0.12p 65 voltage1 beep enable register ? index 17h bit name r/w reset default description 7-2 reserved -- - 0 reserved 1 en_v1_beep r/w 5vsb 0 a one enables the corresponding interrupt status bit for beep output of vin1. 0 reserved -- - 0 reserved voltage protection power good select register ? index 3fh bit name r/w reset default description 7-1 reserved -- - 0 reserved 0 ovp_rst_sel r/w vbat 0 0: ovp/uvp power good signal is 3vccok (3vcc > 2.8v) 1: ovp/uvp power good signal is pwrok. ovp/uvp function wont? start detecting until power good. voltage reading and limit ? index 20h- 3ah address attribute reset default value description 20h r 3vcc -- 3vcc reading. the unit of reading is 8mv. 21h r 3vcc -- vin1 (vcore) reading. the unit of reading is 8mv. 22h r 3vcc -- vin2 reading. the unit of reading is 8mv. 23h r 3vcc -- vin3 reading. the unit of reading is 8mv. 24h r 3vcc -- vin4 reading. the unit of reading is 8mv. 25h r 3vcc -- vsb3v reading. the unit of reading is 8mv. 26h r 3vcc -- vbat reading. the unit of reading is 8mv. 27h r 3vcc -- 5vsb reading. the unit of reading is 8 mv. the 5vsb voltage to be monitored is internally divided by 3. 28h-2ch r -- ff reserved 2dh ro 3vcc -- fan1 present fan duty reading 2eh ro 3vcc -- fan2 present fan duty reading 2fh ro 3vcc -- fan3 present fan duty reading 30 ro vbat 89 3vcc under-voltage protection limit. the unit is 8mv 31 r/w vbat f2 3vcc over-voltage protection limit. the unit is 8 mv 32~35h r ff reserved 36h r/w vbat e2 vin2 over-voltage limit (v2_o vv_limit). the unit is 8mv. (this byte is powered by vbat.) 37h r/w vbat e1 vin3 over-voltage limit (v3_o vv_limit). the unit is 8mv. (this byte is powered by vbat.) 38h r/w vbat 83 vin2 under-voltage limit (v2_u vv_limit). the unit is 8mv (this byte is powered by vbat)
F81867 dec, 2011 v0.12p 66 39h r/w vbat 96 vin3 under-voltage limit (v3_u vv_limit). the unit is 8mv (this byte is powered by vbat) 3ah r/w 5vsb ff vin1 ovp limit. the unit is 8mv (this byte is powered by vbat) 6.4.2.5 fan control setting fan pme# enable register ? index 90h bit name r/w reset default description 7-3 reserved r - 0 reserved 2 en_fan3_pme r/w 5vsb 0 a one enables the corresponding interrupt status bit for pme# interrupt set this bit 1 to enable pme# function for fan3. 1 en_fan2_pme r/w 5vsb 0 a one enables the corresponding interrupt status bit for pme# interrupt. set this bit 1 to enable pme# function for fan2. 0 en_fan1_pme r/w 5vsb 0 a one enables the corresponding interrupt status bit for pme# interrupt. set this bit 1 to enable pme# function for fan1. fan interrupt status register ? index 91h bit name r/w reset default description 7-3 reserved r - 0 reserved 2 fan3_sts r/w 3vcc -- this bit is set when the fan3 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. 1 fan2_sts r/w 3vcc -- this bit is set when the fan2 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. 0 fan1_sts r/w 3vcc -- this bit is set when the fan1 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. fan real time status register ? index 92h bit name r/w reset default description 7-3 reserved -- - 0 reserved 2 fan3_exc r 3vcc -- this bit set to high mean that fan3 count can?t meet the expected count over than smi time (cr9f) or when duty not zero but fan stop over then 3 sec. 1 fan2_exc r 3vcc -- this bit set to high mean that fan2 count can?t meet expect count over than smi time (cr9f) or when duty not zero but fan stop over then 3 sec. 0 fan1_exc r 3vcc -- this bit set to high mean that fan1 count can?t meet expect count over than smi time (cr9f) or when duty not zero but fan stop over then 3 sec.
F81867 dec, 2011 v0.12p 67 fan beep# enable register ? index 93h bit name r/w reset default description 7 reserved - - - reserved 6 full_with_ t2_en r/w 5vsb 0 set one will enable fan to force full speed when t2 over high limit. 5 full_with_ t1_en r/w 5vsb 0 set one will enable fan to force full speed when t1 over high limit. 4 reserved - - - reserved 3 reserved - - - reserved. 2 en_fan3_ beep r/w 5vsb 0 a one enables the corresponding interrupt status bit for beep. 1 en_fan2_ beep r/w 5vsb 0 a one enables the corresponding interrupt status bit for beep. 0 en_fan1_ beep r/w 5vsb 0 a one enables the corresponding interrupt status bit for beep. fan type select register ? index 94h (fan_prog_sel = 0) bit name r/w reset default description 7-6 reserved - - - reserved. 5-4 fan3_type r/w 3vcc 00 00: output pwm mode (push pull) to control fans. 01: use linear fan application circuit to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: reserved. bit 0 is power on trap by fanctrl3 0: fanctrl3 is pull up by external resistor. 1: fanctrl3 is pull down by internal 100k resistor. 3-2 fan2_type r/w 3vcc 00 00: output pwm mode (push pull) to control fans. 01: use linear fan application circuit to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: reserved. bit 0 is power on trap by fanctrl2 0: fanctrl2 is pull up by external resistor. 1: fanctrl2 is pull down by internal 100k resistor.
F81867 dec, 2011 v0.12p 68 1-0 fan1_type r/w 3vcc 00 00: output pwm mode (push pull) to control fans. 01: use linear fan application circuit to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: reserved. bit 0 is power on trap by fanctrl1 0: fanctrl1 is pull up by external resistor. 1: fanctrl1is pull down by internal 100k resistor. s : register default values are decided by trapping. fan1 base temperature register ? offset 94h ( fan_prog_sel = 1) bit name r/w reset default description 7-0 fan1_base _temp r/w 5vsb 0 this register is used to set the base temperature for fan1 temperature adjustment. the fan1 temperature is calculated according to the equation: tfan1 = tnow + (ta ? tb)*ct where tnow is selected by fan1_temp_sel_dig and fan1_temp_sel. tb is this register, ta is selected by tfan1_adj_sel and ct is selected by tfan1_adj_up_rate/tfan1_adj_dn_rate. to access this register, fan_prog_ sel (cr9f[7]) must set to ?1?. fan1 temperature adjustment rate register ? index 95h (fan_prog_sel = 1) bit name r/w reset default description 7 reserved - - - reserved 6-4 tfan1_adj_up _rate 5vsb 3?h0 this selects the weighting of the di fference between ta and tb if ta is higher than tb. 3?h1: 1 (ct = 1) 3?h2: 1/2 (ct= 1/2) 3?h3: 1/4 (ct = 1/4) 3?h4: 1/8 (ct = 1/8) otherwise: 0 to access this byte, fan_pr og_sel must set to ?1?. 3 reserved - - reserved
F81867 dec, 2011 v0.12p 69 2-0 tfan1_adj_dn _rate r/w 5vsb 3?h0 this selects the weighting of the di fference between ta and tb if ta is lower than tb. 3?h1: 1 (ct = 1) 3?h2: 1/2 (ct= 1/2) 3?h3: 1/4 (ct = 1/4) 3?h4: 1/8 (ct = 1/8) otherwise: 0 to access this byte, fan_pr og_sel must set to ?1?. fan mode select register ? index 96h (fan_prog_sel = 0) bit name r/w reset default description 7-6 reserved - - - reserved 5-4 fan3_mode r/w vbat 01 00: auto fan speed control. fan speed wi ll follow different temperature by different rpm defined in 0xc6-0xce. 01: auto fan speed control. fan speed wi ll follow different temperature by different duty cycle defined in 0xc6-0xce. 10: manual mode fan control. user can write expected rpm count to 0xc2-0xc3, and F81867 will adjust duty cycle (pwm fan type) or voltage (linear fan type) to contro l fan speed automatically. 11: manual mode fan control. user can write expected duty cycle (pwm fan type) or voltage (linear fan type) to 0xc3, and F81867 will output this desired duty or voltage to control fan speed. 3-2 fan2_mode r/w vbat 01 00: auto fan speed control. fan speed wi ll follow different temperature by different rpm defined in 0xb6-0xbe. 01: auto fan speed control. fan speed wi ll follow different temperature by different duty cycle (voltage) defined in 0xb6-0xbe. 10: manual mode fan control. user can write expected rpm count to 0xb2-0xb3, and F81867 will adjust duty cycle (pwm fan type) or voltage (linear fan type) to contro l fan speed automatically. 11: manual mode fan control, user can write expected duty cycle (pwm fan type) or voltage (linear fan type) to 0xb3, and F81867 will output this desired duty or voltage to control fan speed.
F81867 dec, 2011 v0.12p 70 1-0 fan1_mode r/w vbat 01 00: auto fan speed control. fan speed wi ll follow different temperature by different rpm defined in 0xa6-0xae. 01: auto fan speed control. fan speed wi ll follow different temperature by different duty cycle defined in 0xa6-0xae. 10: manual mode fan control, user can write expected rpm count to 0xa2-0xa3, and F81867 will auto control duty cycle (pwm fan type) or voltage (linear fan type) to co ntrol fan speed automatically. 11: manual mode fan control, user can write expected duty cycle (pwm fan type) or voltage (linear fan type) to 0xa3, and F81867 will output this desired duty or voltage to control fan speed. fan mode select register ? index 96h (fan_prog_sel = 1) bit name r/w reset default description 7-3 reserved - - - reserved 2-0 tfan1_adj_sel r/w 5vsb 0h this selects which temperature to be used as ta for fan1 temperature adjustment. 000: peci (cr7eh) 001: t1 (cr72h) 010: t2 (cr74h) 011: t3 (cr76h) 100: ibx/tsi cpu temperature (cr7ah) 101:ibx pch temperature (cr7bh). 110: ibx mch temperature (cr7ch). 111: ibx maximum temperature (cr7dh). otherwise: ta will be 0. to access this register fan_ prog_sel must set to ?1?. faster fan filter control register ? index 97h bit name r/w reset default description 7-3 reserved - - - reserved. 2 flt_fast3 r/w 5vsb 0 set this bit 1 if fan3 is using a faster fan. 1 flt_fast2 r/w 5vsb 0 set this bit 1 if fan2 is using a faster fan. 0 flt_fast1 r/w 5vsb 0 set this bit 1 if fan1 is using a faster fan.
F81867 dec, 2011 v0.12p 71 auto fan1 and fan2 boundary hystersis select register ? index 98h bit name r/w reset default description 7-4 fan2_hys r/w 5vsb 4h boundary hysteresis. (0~15 o c) segment will change when the temperature over the boundary temperature and below the (boundary ? hysteresis). 3-0 fan1_hys r/w 5vsb 4h boundary hysteresis. (0~15 o c) segment will change when the temperature over the boundary temperature and below the (boundary ? hysteresis). auto fan3 boundary hystersis select register ? index 99h bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 fan3_hys r/w 5vsb 2h boundary hysteresis. (0~15 o c) segment will change when the temperature over the boundary temperature and below the (boundary ? hysteresis). fan3 control register ? index 9ah bit name r/w reset default description 7 reserved - - - reserved. 6 freq_sel_add3 r/w 5vsb 0 this bit and fan3_pwm_freq_sel are used to select fan3 pwm frequency. new_freq_sel3 = { freq_sel_add3, fan3_pwm_freq_sel} 00: 23.5 khz 01: 11.75 khz 10: 5.875 khz 11: 220 hz 5 freq_sel_add2 r/w 5vsb 0 this bit and fan2_pwm_freq_sel are used to select fan2 pwm frequency. new_freq_sel2 = { freq_sel_add2, fan2_pwm_freq_sel} 00: 23.5 khz 01: 11.75 khz 10: 5.875 khz 11: 220 hz
F81867 dec, 2011 v0.12p 72 4 freq_sel_add1 r/w 5vsb 0 this bit and fan1_pwm_freq_sel are used to select fan1 pwm frequency. new_freq_sel1 = { freq_sel_add1, fan1_pwm_freq_sel} 00: 23.5 khz 01: 11.75 khz 10: 5.875 khz 11: 220 hz 3-2 reserved r/w - 0 reserved (keep the value of these two bits ?0?) 1-0 reserved - - - reserved auto fan up speed update rate select register ? index 9bh (fan_prog_sel = 0) bit name r/w reset default description 7-6 reserved - - - reserved. 5-4 fan3_up_rate r/w 5vsb 01 fan3 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 3-2 fan2_up_rate r/w 5vsb 01 fan2 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 1-0 fan1_up_rate r/w 5vsb 01 fan1 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz auto fan down speed update rate select register ? index 9bh (fan_prog_sel = 1) bit name r/w reset default description 7 up_dn_rate_en r/w 5vsb 0 0: fan down rate disable 1: fan down rate enable set this bit 1 to use different fan up/dow n rate. if this bit is not set to 1, the fan up/down rate will follow fan_up_rate. 6 direct_load_en r/w 5vsb 0 0: direct load disable 1: direct load enable for manual duty mode
F81867 dec, 2011 v0.12p 73 5-4 fan3_dn_rate r/w 5vsb 01 fan3 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 3-2 fan2_dn_rate r/w 5vsb 01 fan2 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 1-0 fan1_dn_rate r/w 5vsb 01 fan1 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz fan1 and fan2 start up duty-cycle/voltage ? index 9ch bit name r/w reset default description 7-4 fan2_stop _duty r/w 5vsb 5h when fan start, the fan_ctrl2 will increase duty-cycle from 0 to this (value x 8) directly. and if fan speed is down, the fan_ctrl 2 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). 3-0 fan1_stop _duty r/w 5vsb 5h when fan start, the fan_ctrl 1 will increase duty-cycle from 0 to this (value x 8 directly. and if fan speed is down, the fan_ctrl 1 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). fan3 start up duty-cycle/voltage ? index 9dh bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 fan3_stop_ duty r/w 5vsb 5h when fan start, the fan_ctrl 3 will increase duty-cycle from 0 to this (value x 8 directly. and if fan speed is down, the fan_ctrl 3 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4).
F81867 dec, 2011 v0.12p 74 fan programmable duty-cycle/voltage loaded after power-on ? index 9eh bit name r/w reset default description 7-0 prog_duty_val r/w 5vsb 66h this byte will be immediately loaded as fan duty value after vdd is powered on if it has been programmed before shut down. fan fault time register ? index 9fh bit name r/w reset default description 7 fan_prog_sel r/w 5vsb 0 set this bit to ?1? will enable accessing registers of other bank. 6 fan_mnt_sel r/w 5vsb 0 set this bit to monitor a slower fan. 5 reserved - - - reserved 4 full_duty_sel r/w 3vcc - 0: the fan duty is 100% and will be loaded immediately after vdd is powered on if cr9e is not been programmed before shut down. (pull down by external resistor) 1: the fan duty is 40% and will be loaded immediately after vdd is powered on if cr9e is not been programmed before shut down. (pull up by internal 47k a. fan1 index a0h~afh address attribute reset default description a0h ro 3vcc 8?h0f fan1 count reading (msb). at the mom ent of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. a1h ro 3vcc 8?hff fan1 count reading (lsb).
F81867 dec, 2011 v0.12p 75 a2h r/w vbat 8?h00 rpm mode(cr96 bit0=0): fan1 expect speed count value (msb), in auto fan mode (cr96 bit1 ? 0) this register is auto updated by hardware. duty mode(cr96 bit0=1): this byte is reserved byte. a3h r/w vbat 8?h01 rpm mode(cr96 bit0=0): fan1 expect speed count value (lsb) or expect pwm duty, in auto fan mode this register is auto updated by hardware and read only. duty mode(cr96 bit0=1): the value programming in this byte is duty value. in auto fan mode (cr96 bit1 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% a4h r/w 5vsb 8?h03 fan1 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. a5h r/w 5vsb 8?hff fan1 full speed count reading (lsb). vt1 boundary 1 temperature ? index a6h bit name r/w reset default description 7-0 bound1tmp1 r/w 5vsb 3ch (60 o c) the first boundary temperature for vt1 in temperature mode. when vt1 temperature exceeds this boundary, expected fan1 value will be loaded from segment 1 register (index aah). when vt1 temperature is under this boundary ? hysteresis, expected fan1 value will be loaded from segment 2 register (index abh). this byte is a 2?s complement value ranged from -128 o c ~ 127 o c. vt1 boundary 2 temperature ? index a7 bit name r/w reset default description 7-0 bound2tmp1 r/w 5vsb 32 (50 o c) the 2nd boundary temperature for vt1 in temperature mode. when vt1 temperature is exceed this boundary, fan1 expected value will load from segment 2 register (index abh). when vt1 temperature is below this boundary ? hysteresis, fan1 expected value will load from segment 3 register (index ach). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c.
F81867 dec, 2011 v0.12p 76 vt1 boundary 3 temperature ? index a8h bit name r/w reset default description 7-0 bound3tmp1 r/w 5vsb 28h (40 o c) the 3rd boundary temperature fo r vt1 in temperature mode. when vt1 temperature is exceed this boundary, fan1 expected value will load from segment 3 register (index ach). when vt1 temperature is below this boundary ? hysteresis, fan1 expected value will load from segment 4 register (index adh). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. vt1 boundary 4 temperature ? index a9 bit name r/w reset default description 7-0 bound4tmp1 r/w 5vsb 1eh (30 o c) the 4th boundary temperature fo r vt1 in temperature mode. when vt1 temperature is exceed this boundary, fan1 expected value will load from segment 4 register (index adh). when vt1 temperature is below this boundary ? hysteresis, fan1 expected value will load from segment 5 register (index aeh). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. fan1 segment 1 speed count ? index aah bit name r/w reset default description 7 - 0 sec1speed1 r / w 5vsb ffh (100%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. ex: 100%:full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ( (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 segment 2 speed count ? index abh bit name r/w reset default description 7-0 sec2speed1 r/w 5vsb d9h (85%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section.
F81867 dec, 2011 v0.12p 77 fan1 segment 3 speed count register ? index ach bit name r/w reset default description 7-0 sec3speed1 r/w 5vsb b2h (70%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 segment 4 speed count register ? index adh bit name r/w reset default description 7-0 sec4speed1 r/w 5vsb 99h (60%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 segment 5 speed count register ? index aeh bit name r/w reset default description 7-0 sec5peed1 r/w 5vsb 80h (50%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 temperature mapping select ? index afh bit name r/w reset default description 7 fan1_temp _sel_dig r/w 5vsb 0 this bit companies with fan1_temp_sel select the temperature source for controlling fan1. 6 fan1_pwm _freq_sel r/w 5vsb 0 this bit and freq_sel_add1 are used to select fan1 pwm frequency. new_freq_sel1 = { freq_sel_add1, fan1_pwm_freq_sel} 00: 23.5 khz 01: 11.75 khz 10: 5.875 khz 11: 220 hz 5 fan1_up_t_en r/w 5vsb 0 set 1 to force fan1 to full speed if any temperature over its high limit.
F81867 dec, 2011 v0.12p 78 4 fan1_ interpolation_e n r/w 5vsb 1 set 1 will enable the interpolat ion of the fan expect table. 3 fan1_jump _high_en r/w 5vsb 1 this register controls the fan1 dut y movement when temperature over highest boundary. 0: the fan1 duty will increases with the slope selected by fan1_rate_sel register. 1: the fan1 duty will directly jumps to the value of sec1speed1 register. this bit only activates in duty mode. 2 fan1_jump _low_en r/w 5vsb 1 this register controls the fan1 dut y movement when temperature under (highest boundary ? hysteresis). 0: the fan1 duty will decreases with the slope selected by fan1_rate_sel register. 1: the fan1 duty will directly jumps to the value of sec2speed1 register. this bit only activates in duty mode. 1 - 0 fan1_temp_sel r / w 5vsb 01 this registers company with fan1_temp_sel_dig select the temperature source for controlling fan1. the following value is comprised by {fan1_temp_sel_dig, fan1_temp_sel} 000: fan1 follows peci temperature (cr7eh) 001: fan1 follows temperature 1 (cr72h). 010: fan1 follows temperature 2 (cr74h). 011: fan1 follows temperature 0 (cr70h). 100: fan1 follows ibx/tsi cpu temperature (cr7ah) 101: fan1 follows ibx pch temperature (cr7bh). 110: fan1 follows ibx mch temperature (cr7ch). 111: fan1 follows ibx maximum temperature (cr7dh). others are reserved. b. fan2 index b0h~bfh address attribute reset default value description b0h ro 3vcc 8?h0f fan2 count reading (msb). at the mo ment of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. b1h ro 3vcc 8?hff fan2 count reading (lsb).
F81867 dec, 2011 v0.12p 79 b2h r/w vbat 8?h00 rpm mode(cr96 bit2=0): fan2 expect speed count value (msb), in auto fan mode(cr96 bit3 ? 0) this register is auto updated by hardware. duty mode (cr96 bit2=1): this byte is reserved byte. b3h r/w vbat 8?h01 rpm mode(cr96 bit2=0): fan2 expect speed count value (lsb) or expect pwm duty , in auto fan mode this register is auto updated by hardware and read only. duty mode(cr96 bit2=1): the value programming in this byte is duty value. in auto fan mode (cr96 bit3 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% b4h r/w 5vsb 8?h03 fan2 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. b5h r/w 5vsb 8?hff fan2 full speed count reading (lsb). vt2 boundary 1 temperature ? index b6h bit name r/w reset default description 7-0 bound1tmp2 r/w 5vsb 3ch (60 o c) the first boundary temperature for vt2 in temperature mode. when vt2 temperature exceeds this boundary, fan2 expect value will load from segment 1 register (index bah). when vt2 temperature is under this boundary ? hysteresis, fan2 expect value will load from segment 2 register (index bah). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. vt2 boundary 2 temperature ? index b7 bit name r/w reset default description 7-0 bound2tmp2 r/w 5vsb 32 (50 o c) the 2nd boundary temperature for vt2 in temperature mode. when vt2 temperature is exceed this boundary, fan2 expected value will load from segment 2 register (index bbh). when vt2 temperature is below this boundary ? hysteresis, fan2 expected value will load from segment 3 register (index bch). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c.
F81867 dec, 2011 v0.12p 80 vt2 boundary 3 temperature ? index b8h bit name r/w reset default description 7-0 bound3tmp2 r/w 5vsb 28h (40 o c) the 3rd boundary temperature fo r vt2 in temperature mode. when vt2 temperature is exceed this boundary, fan2 expected value will load from segment 3 register (index bch). when vt2 temperature is below this boundary ? hysteresis, fan2 expected value will load from segment 4 register (index bdh). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. vt2 boundary 4 temperature ? index b9 bit name r/w reset default description 7-0 bound4tmp2 r/w 5vsb 1eh (30 o c) the 4th boundary temperature fo r vt2 in temperature mode. when vt2 temperature is exceed this boundary, fan2 expected value will load from segment 4 register (index bdh). when vt2 temperature is below this boundary ? hysteresis, fan2 expected value will load from segment 5 register (index beh). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. fan2 segment 1 speed count ? index bah bit name r/w reset default description 7 - 0 sec1speed2 r / w 5vsb ffh (100%) the meaning of this register is depending on the fan2_mode (cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. ex: 100%:full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ? (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 segment 2 speed count ? index bbh bit name r/w reset default description 7 - 0 sec2speed2 r / w 5vsb d9h (85%) the meaning of this register is depending on the fan2_mode (cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section.
F81867 dec, 2011 v0.12p 81 fan2 segment 3 speed coun t register ? index bch bit name r/w reset default description 7 - 0 sec3speed2 r / w 5vsb b2h (70%) the meaning of this register is depending on the fan2_mode (cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 segment 4 speed coun t register ? index bdh bit name r/w reset default description 7 - 0 sec4speed2 r / w 5vsb 99h (60%) the meaning of this register is depending on the fan2_mode (cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 segment 5 speed count register ? index beh bit name r/w reset default description 7 - 0 sec5peed2 r / w 5vsb 80h (50%) the meaning of this register is depending on the fan2_mode (cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 temperature mapping select ? index bfh bit name r/w reset default description 7 fan2_temp_ sel_dig r/w 5vsb 0 this bit companies with fan2_temp_sel to select the temperature source for controlling fan2. 6 fan2_pwm_ freq_sel r/w 5vsb 0 this bit and freq_sel_add2 are used to select fan2 pwm frequency. new_freq_sel2 = { freq_sel_add2, fan2_pwm_freq_sel} 00: 23.5 khz 01: 11.75 khz 10: 5.875 khz 11: 220 hz 5 fan2_up_t_en r / w 5vsb 0 set 1 to force fan2 to full speed if any temperature over its high limit.
F81867 dec, 2011 v0.12p 82 4 fan2_ interpolation_en r/w 5vsb 1 set 1 will enable the interpolat ion of the fan expect table. 3 fan2_jump_ high_en r/w 5vsb 1 this register controls the fan2 dut y movement when temperature over highest boundary. 0: the fan2 duty will increases with the slope selected by fan2_rate_sel register. 1: the fan2 duty will directly jumps to the value of sec1speed2 register. this bit only activates in duty mode. 2 fan2_jump_ low_en r/w 5vsb 1 this register controls the fan2 duty movement when temperature under (highest boundary ? hysteresis). 0: the fan2 duty will decreases with the slope selected by fan2_rate_sel register. 1: the fan2 duty will directly jumps to the value of sec2speed2 register. this bit only activates in duty mode. 1 - 0 fan2_temp_sel r / w 5vsb 10 this registers companying with fan2_temp_sel_dig select the temperature source for controlling fan2. the following value is comprised by {fan2_temp_sel_dig, fan2_temp_sel} 000: fan2 follows peci temperature (cr7eh) 001: fan2 follows temperature 1 (cr72h). 010: fan2 follows temperature 2 (cr74h). 011: fan2 follows temperature 0 (cr70h). 100: fan2 follows ibex/tsi cpu temperature (cr7ah) 101: fan2 follows ibex pch temperature (cr7bh). 110: fan2 follows ibex mch temperature (cr7ch). 111: fan2 follows ibex maximum temperature (cr7dh). otherwise: reserved. c. fan3 index c0h- cfh address attribute reset default value description c0h ro 3vcc 8?h0f fan3 count reading (msb). at the mo ment of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. c1h ro 3vcc 8?hff fan3 count reading (lsb).
F81867 dec, 2011 v0.12p 83 c2h r/w vbat 8?h00 rpm mode(cr96 bit4=0): fan3 expect speed count value (msb), in auto fan mode (cr96 bit5 ? 0) this register is auto updated by hardware. duty mode(cr96 bit4=1): this byte is reserved byte. c3h r/w vbat 8?h01 rpm mode(cr96 bit4=0): fan3 expect speed count value (lsb) or expect pwm duty, in auto fan mode this register is auto updated by hardware and read only. duty mode(cr96 bit4=1): the value programming in this byte is duty value. in auto fan mode (cr96 bit5 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% c4h r/w 5vsb 8?h03 fan3 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. th is will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. c5h r/w 5vsb 8?hff fan3 full speed count reading (lsb). vt3 boundary 1 temperature ? index c6h bit name r/w reset default description 7-0 bound1tmp3 r/w 5vsb 3ch (60 o c) the first boundary temperature for vt3 in temperature mode. when vt3 temperature exceeds this boundary, fan3 expect value will load from segment 1 register (index cah). when vt3 temperature is under this boundary ? hysteresis, fan3 expect value will load from segment 2 register (index cah). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. vt3 boundary 2 temperature ? index c7 bit name r/w reset default description 7-0 bound2tmp3 r/w 5vsb 32 (50 o c) the 2nd boundary temperature for vt3 in temperature mode. when vt3 temperature is exceed this boundary, fan3 expected value will load from segment 2 register (index cbh). when vt3 temperature is below this boundary ? hysteresis, fan3 expected value will load from segment 3 register (index cch). this byte is a 2?s complement value ranging from-128 o c ~ 127 o c.
F81867 dec, 2011 v0.12p 84 vt3 boundary 3 temperature ? index c8h bit name r/w reset default description 7-0 bound3tmp3 r/w 5vsb 28h (40 o c) the 3rd boundary temperature fo r vt3 in temperature mode. when vt3 temperature is exceed this boundary, fan3 expected value will load from segment 3 register (index cch). when vt3 temperature is below this boundary ? hysteresis, fan3 expected value will load from segment 4 register (index cdh). this byte is a 2?s complement value ranging from-128 o c ~ 127 o c. vt3 boundary 4 temperature ? index c9h bit name r/w reset default description 7-0 bound4tmp3 r/w 5vsb 1eh (30 o c) the 4th boundary temperature fo r vt3 in temperature mode. when vt3 temperature is exceed this boundary, fan3 expected value will load from segment 4 register (index cdh). when vt3 temperature is below this boundary ? hysteresis, fan3 expected value will load from segment 5 register (index ceh). this byte is a 2?s complement value ranging from-128 o c ~ 127 o c. fan3 segment 1 speed count ? index cah bit name r/w reset default description 7 - 0 sec1speed3 r / w 5vsb ffh (100%) the meaning of this register is depending on the fan3_mode (cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. ex:100%:full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ( (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan3 segment 2 speed count ? index cbh bit name r/w reset default description 7-0 sec2speed3 r/w 5vsb d9h (85%) the meaning of this register is depending on the fan3_mode (cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section.
F81867 dec, 2011 v0.12p 85 fan3 segment 3 speed count ? index cch bit name r/w reset default description 7-0 sec3speed3 r/w 5vsb b2h (70%) the meaning of this register is depending on the fan3_mode (cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan3 segment 4 speed count ? index cdh bit name r/w reset default description 7-0 sec4speed3 r/w 5vsb 99h (60%) the meaning of this register is depending on the fan3_mode (cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan3 segment 5 speed count ? index ceh bit name r/w reset default description 7-0 sec5speed3 r/w 5vsb 80h (50%) the meaning of this register is depending on the fan3_mode (cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan3 temperature mapping select ? index cfh bit name r/w reset default description 7 fan3_temp_ sel_dig r/w 5vsb 0 this bit companies with fan3_temp_sel select the temperature source for controlling fan3. 6 fan3_pwm_ freq_sel r/w 5vsb 0 this bit and freq_sel_add3 are used to select fan3 pwm frequency. new_freq_sel3 = { freq_sel_add3, fan3_pwm_freq_sel} 00: 23.5 khz 01: 11.75 khz 10: 5.875 khz 11: 220 hz 5 fan3_up_t_en r / w 5vsb 0 set 1 to force fan3 to full speed if any temperature over its high limit. 4 fan3_ interpolation_en r/w 5vsb 1 set 1 will enable the interpolat ion of the fan expect table.
F81867 dec, 2011 v0.12p 86 3 fan3_jump_ high_en r/w 5vsb 1 this register controls the fan3 dut y movement when temperature over highest boundary. 0: the fan3 duty will increases with the slope selected by fan3_rate_sel register. 1: the fan3 duty will directly jumps to the value of sec1speed3 register. this bit only activates in duty mode. 2 fan3_jump_ low_en r/w 5vsb 1 this register controls the fan3 duty movement when temperature under (highest boundary ? hysteresis). 0: the fan3 duty will decreases with the slope selected by fan3_rate_sel register. 1: the fan3 duty will directly jumps to the value of sec2speed3 register. this bit only activates in duty mode. 1 - 0 fan3_temp_sel r / w 5vsb 11 this registers companying with fan3_temp_sel_dig select the temperature source for controlling fan3. the following value is comprised by {fan3_temp_sel_dig, fan3_temp_sel} 000: fan3 follows peci temperature (cr7eh) 001: fan3 follows temperature 1 (cr72h). 010: fan3 follows temperature 2 (cr74h). 011: fan3 follows temperature 0 (cr70h). 100: fan3 follows ibex/tsi cpu temperature (cr7ah) 101: fan3 follows ibex pch temperature (cr7bh). 110: fan3 follows ibex mch temperature (cr7ch). 111: fan3 follows ibex maximum temperature (cr7dh). otherwise: reserved. 6.5 keyboard controller the kbc circuit provides the functions inclu ded a keyboard and/or a ps/2 mouse, and can be used with ibm-compatible personal computers or ps /2-based systems. the controller receives serial data from the keyboard or ps/2 mouse, checks t he parity of the data, and presents the data to the system as a byte of data in its output buffer. the c ontroller will assert an interrupt to the system when data are placed in its output buffer. output buffer the output buffer is an 8-bit read-only register at i/o address 60h. the keyboard controller uses the output buffer to send the code receiv ed from the keyboard and data bytes required by
F81867 dec, 2011 v0.12p 87 commands to the system. input buffer the input buffer is an 8-bit write-only register at i/o address 60h or 64h. writing to address 60h sets a flag to indicate a data write; writing to address 64h sets a flag to indicate a command write. data written to i/o address 60h is sent to keyboard through the controller's input buffer only if the input buffer full bit in the status register is ?0?. status register the status register is an 8-bit read-only register at i/o address 64h that holds information about the status of the keyboard controller and interface. it may be read at any time. bit bit function description 0 output buffer full 0: output buffer empty 1: output buffer full 1 input buffer full 0: input buffer empty 1: input buffer full 2 system flag this bit may be set to 0 or 1 by wr iting to the system flag bit in the command byte of the keyboard controller (kccb). it defaults to 0 after a power-on reset. 3 command/data 0: data byte 1: command byte 4 inhibit switch 0: keyboard is inhibited 1: keyboard is not inhibited 5 mouse output buffer 0: muse output buffer empty 1: mouse output buffer full 6 general purpose time-out 0: no time-out error 1: time-out error 7 parity error 0: odd parity 1: even parity (error) commands command function 20h read command byte
F81867 dec, 2011 v0.12p 88 60h write command byte bit description 0 enable keyboard interrupt 1 enable mouse interrupt 2 system flag 3 reserve 4 disable keyboard interface 5 disable mouse interface 6 ibm keyboard translate mode 7 reserve a7h disable auxiliary device interface a8h enable auxiliary device interface a9h auxiliary interface test 8?h00: indicate auxiliary interface is ok. 8?h01: indicate auxiliary clock is low. 8?h02: indicate auxiliary clock is high 8?h03: indicate auxiliary data is low 8?h04: indicate auxiliary data is high aah self-test return 55h if self test succeeds abh keyboard interface test 8?h00: indicate keyboard interface is ok. 8?h01: indicate keyboard clock is low. 8?h02: indicate keyboard clock is high 8?h03: indicate keyboard data is low 8?h04: indicate keyboard data is high adh disable keyboard interface aeh enable keyboard interface c0h read input port(p1) and send data to the system c1h continuously puts the lower four bits of port1 into status register c2h continuously puts the upper four bits of port1 into status register cah read the data written by cbh command. cbh written a scratch data. this byte could be read by cah command. d0h send port2 value to the system d1h only set/reset gatea20 line based on the system data bit 1 d2h send data back to the system as if it came from keyboard d3h send data back to the system as if it came from muse d4h output next received byte of data from system to mouse feh low pulse on kbrst# about 6 s kbc command description
F81867 dec, 2011 v0.12p 89 ps/2 wakeup function the kbc supports keyboard and mouse wakeup function. kbc will assert pme or pwsout# signal. those wakeup conditions are cont rolled by the configuration register. 6.6 gpio F81867 has 72 pins gpio in total. all gpio supports digi t io for input/output control, output data control, input status and high/low level/pulse, open drain/push pull function selection. the gpio0x and gpio1x support interrupt status. the gpio0x, gpio1x, gpio5x, and gpio 8x have different sirq cha nnels. the gpio8x supports scan code function, please see regist ers for detail. please see below for gpio access methods and status: 6.6.1 gpio access method there are nine sets of gpio in F81867 wh ich can be accessed by three ways as below: 1. configuration register port: use 0x4e/0x4f (or 0x2e/0x2f) port with logic device number 0x06. please refer to configuration register for detail. 2. index/data port: the index port is base addres s + 0 and data port is base address + 1. to access the gpio register, user should first write index to index port and then read/write from/to data port. the index for each register is same as the definition in configuration register. 3. digital i/o: this way could access gpio data re gister only. it is used for quickly control the gpio pins. the register for each address is as list: *available when gpio_dec_range is set ?1? (configuration register index 0x27, bit 5) gpio digital i/o registers offset register name default value msb lsb 0h index port 1 1 1 1 1 1 1 1 1h data port - - - - - - - - 2h gpio8 data port - - - - - - - - 3h gpio7 data port - - - - - - - - 4h gpio6 data port - - - - - - - - 5h gpio5 data port - - - - - - - - 6h gpio0 data port - - - - - - - - 7h gpio1 data port - - - - - - - - 8h* gpio2 data port - - - - - - - - 9h* gpio3 data port - - - - - - - - ah* gpio4 data port - - - - - - - - b-fh* reserved - - - - - - - -
F81867 dec, 2011 v0.12p 90 gpio8 data port ? offset 02h bit name r/w reset default description 7-0 gpio8_data r/w lreset# - gpio8 data control write data to this byte will change the value of gpio80_val ~ gpio87_val in configuration register as writing data to index 0x89. read data from this byte will read the pin status of gpio80_in ~ gpio87_in as the value in index 0x8a gpio7 data port ? offset 03h bit name r/w reset default description 7-0 gpio7_data r/w lreset# - gpio7 data control write data to this byte will change the value of gpio70_val ~ gpio77_val in configuration register as writing data to index 0x81. read data from this byte will read the pin status of gpio70_in ~ gpio77_in as the value in index 0x82 gpio6 data port ? offset 04h bit name r/w reset default description 7-0 gpio6_data r/w lreset# - gpio6 data control write data to this byte will change the value of gpio60_val ~ gpio67_val in configuration register as writing data to index 0x91. read data from this byte will read the pin status of gpio60_in ~ gpio67_in as the value in index 0x92 gpio5 data port ? offset 05h bit name r/w reset default description 7-0 gpio5_data r/w lreset# - gpio5 data control write data to this byte will change the value of gpio50_val ~ gpio57_val in configuration register as writing data to index 0xa1. read data from this byte will read the pin status of gpio50_in ~ gpio57_in as the value in index 0xa2 gpio0 data port ? offset 06h bit name r/w reset default description 7-0 gpio0_data r/w 5vsb - gpio0 data control write data to this byte will change the value of gpio00_val ~ gpio07_val in configuration register as writing data to index 0xf1. read data from this byte will read the pin status of gpio00_in ~ gpio07_in as the value in index 0xf2 gpio1 data port ? offset 07h bit name r/w reset default description 7-0 gpio1_data r/w 5vsb - gpio1 data control write data to this byte will change the value of gpio10_val ~ gpio17_val in configuration register as writing data to index 0xe1. read data from this byte will read the pin status of gpio10_in ~ gpio17_in as the value in index 0xe2
F81867 dec, 2011 v0.12p 91 *gpio2 data port ? offset 08h bit name r/w reset default description 7-0 gpio2_data r/w 5vsb - gpio2 data control, this byte is available when gpiodec_range is set. write data to this byte will change the value of gpio20_val ~ gpio27_val in configuration register as writing data to index 0xd1. read data from this byte will read the pin status of gpio20_in ~ gpio27_in as the value in index 0xd2 *gpio3 data port ? offset 09h bit name r/w reset default description 7-0 gpio3_data r/w lreset# - gpio3 data control, this byte is available when gpiodec_range is set. write data to this byte will change the value of gpio30_val ~ gpio37_val in configuration register as writing data to index 0xc1. read data from this byte will read the pin status of gpio30_in ~ gpio37_in as the value in index 0xc2 gpio4 data port ? offset 0ah bit name r/w reset default description 7-0 gpio4_data r/w lreset# - gpio4 data control, this byte is available when gpiodec_range is set. write data to this byte will change the value of gpio40_val ~ gpio47_val in configuration register as writing data to index 0xb1. read data from this byte will read the pin status of gpio40_in ~ gpio47_in as the value in index 0xb2 6.6.2 gpiox status z means high impendence. if the external circuit is pull high then the pin status is "h"; else if the external circuit is pull low then the pin status is "l". user define means by programming the configure register. gpio0x g3 -> s5 s0 s3 s5 52 gpio00 l user define user define user define i _ vsb3v 5vsb i _ vsb3v 53 gpio01 l user define user define user define i _ vsb3v 5vsb i _ vsb3v 54 gpio02 z user define user define user define i _ vsb3v 5vsb i _ vsb3v 55 gpio03 l user define user define user define i _ vsb3v 5vsb i _ vsb3v 56 gpio04 z user define user define user define i _ vsb3v 5vsb i _ vsb3v 57 gpio05 z user define user define user define i _ vsb3v 5vsb i _ vsb3v 58 gpio06 z user define user define user define i _ vsb3v 5vsb i _ vsb3v 59 gpio07 z user define user define user define i_vsb3v 5vsb i_vsb3v pin status pin name register power well pin power well register reset signal
F81867 dec, 2011 v0.12p 92 gpio1x g3 -> s5 s0 s3 s5 65 gpio10 z user define user define user define i_vsb3v 5vsb i_vsb3v 66 gpio11 z user define user define user define i _ vsb3v 5vsb i _ vsb3v 67 gpio12 z user define user define user define i _ vsb3v 5vsb i _ vsb3v 68 gpio13 z user define user define user define i _ vsb3v 5vsb i _ vsb3v 69 gpio14 z user define user define user define i _ vsb3v 5vsb i _ vsb3v 70 gpio15 z user define user define user define i _ vsb3v 5vsb i _ vsb3v 71 gpio16 z user define user define user define i _ vsb3v 5vsb i _ vsb3v 72 gpio17 z user define user define user define i_vsb3v 5vsb i_vsb3v pin status pin name register power well pin power well register reset signal gpio2x g3 -> s5 s0 s3 s5 76 gpio20 z user define user define user define i_vsb3v 5vsb i_vsb3v 77 gpio21 z user define user define user define i _ vsb3v 5vsb i _ vsb3v 78 gpio22 z user define user define user define i _ vsb3v 5vsb i _ vsb3v 79 gpio23 z user define user define user define i _ vsb3v 5vsb i _ vsb3v 80 gpio24 z user define user define user define i _ vsb3v 5vsb i _ vsb3v 81 gpio25 z user define user define user define i _ vsb3v 5vsb i _ vsb3v 82 gpio26 l user define user define user define i _ vsb3v 5vsb vbat 83 gpio27 l user define user define user define i_vsb3v 5vsb vbat pin status pin name register power well pin power well register reset signal * gpio26 and gpio27 have no push pull function. gpio3x g3 -> s5 s0 s3 s5 36 gpio30 z user define z z i_vsb3v lreset# 3vcc 37 gpio31 z user define z z i _ vsb3v lreset# 3vcc 38 gpio32 z user define z z i _ vsb3v lreset# 3vcc 39 gpio33 z user define z z i _ vsb3v lreset# 3vcc 40 gpio34 z user define z z i _ vsb3v lreset# 3vcc 41 gpio35 z user define z z i _ vsb3v lreset# 3vcc 42 gpio36 z user define z z i _ vsb3v lreset# 3vcc 43 gpio37 z user define z z i_vsb3v lreset# 3vcc pin status pin name register power well pin power well register reset signal
F81867 dec, 2011 v0.12p 93 gpio4x g3 -> s5 s0 s3 s5 44 gpio40 z user define z z i_vsb3v lreset# 3vcc 45 gpio41 z user define z z i _ vsb3v lreset# 3vcc 46 gpio42 z user define z z i _ vsb3v lreset# 3vcc 47 gpio43 z user define z z i _ vsb3v lreset# 3vcc 48 gpio44 z user define z z i _ vsb3v lreset# 3vcc 49 gpio45 z user define z z i _ vsb3v lreset# 3vcc 50 gpio46 z user define z z i _ vsb3v lreset# 3vcc 51 gpio47 z user define z z i_vsb3v lreset# 3vcc pin status pin name register power well pin power well register reset signal gpio5x g3 -> s5 s0 s3 s5 9 gpio50 z user define z z i_vsb3v lreset# 3vcc 10 gpio51 z user define z z i_vsb3v lreset# 3vcc 11 gpio52 z user define z z i_vsb3v lreset# 3vcc 12 gpio53 z user define z z i_vsb3v lreset# 3vcc 13 gpio54 z user define z z i_vsb3v lreset# 3vcc 14 gpio55 z user define z z i_vsb3v lreset# 3vcc 15 gpio56 z user define z z i_vsb3v lreset# 3vcc 16 gpio57 z user define z z i_vsb3v lreset# 3vcc pin status pin name register power well pin power well register reset signal gpio6x g3 -> s5 s0 s3 s5 17 gpio60 z user define z z i_vsb3v lreset# 3vcc 18 gpio61 z user define z z i_vsb3v lreset# 3vcc 19 gpio62 z user define z z i_vsb3v lreset# 3vcc 20 gpio63 z user define z z i_vsb3v lreset# 3vcc 21 gpio64 z user define z z i _ vsb3v lreset# 3vcc 74 gpio65 z user define z z i _ vsb3v lreset# * i _ vsb3v 86 gpio66 l user define z z i _ vsb3v lreset# * vbat 87 gpio67 z user define z z i_vsb3v lreset# * vbat pin status pin name register power well pin power well register reset signal * gpio66 and gpio67 have no push pull function.
F81867 dec, 2011 v0.12p 94 gpio7x g3 -> s5 s0 s3 s5 103 gpio70 z user define z z i_vsb3v lreset# 3vcc 104 gpio71 z user define z z i _ vsb3v lreset# 3vcc 105 gpio72 z user define z z i _ vsb3v lreset# 3vcc 106 gpio73 z user define z z i _ vsb3v lreset# 3vcc 107 gpio74 z user define z z i _ vsb3v lreset# 3vcc 108 gpio75 z user define z z i _ vsb3v lreset# 3vcc 109 gpio76 z user define z z i _ vsb3v lreset# 3vcc 110 gpio77 z user define z z i_vsb3v lreset# 3vcc pin status pin name register power well pin power well register reset signal gpio8x g3 -> s5 s0 s3 s5 111 gpio80 z user define z z i_vsb3v lreset# 3vcc 112 gpio81 z user define z z i _ vsb3v lreset# 3vcc 113 gpio82 z user define z z i _ vsb3v lreset# 3vcc 114 gpio83 z user define z z i _ vsb3v lreset# 3vcc 115 gpio84 z user define z z i _ vsb3v lreset# 3vcc 116 gpio85 z user define z z i _ vsb3v lreset# 3vcc 117 gpio86 z user define z z i _ vsb3v lreset# 3vcc 118 gpio88 z user define z z i_vsb3v lreset# 3vcc pin status pin name register power well pin power well register reset signal 6.7 watchdog timer function watch dog timer is provided for system controlling. if time -out can trigger one signal to high/low level/pulse, the signal is depend on register setting. the time unit has two ways from 1sec or 60sec. in pulse mode, there are four pulse widths can be selected (1ms/25ms/125ms/5sec). others, please refer the device register description as below. watchdog timer configuration register 1 ? base address + 05h bit name r/w reset default description 7 reserved r - 0 reserved 6 wdtmout_sts r/w 5vsb 0 if watchdog timeout event occurred, this bit will be set to 1. write a 1 to this bit will clear it to 0. 5 wd_en r/w 5vsb 0 if this bit is set to 1, the counting of watchdog time is enabled. 4 wd_pulse r/w 5vsb 0 select output mode (0: level, 1: pulse) of rstout# by setting this bit. 3 wd_unit r/w 5vsb 0 select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit. 2 wd_hactive r/w 5vsb 0 select output polarity of rstout# (1: high active, 0: low active) by setting this bit. 1-0 wd_pswidth r/w 5vsb 0 select output pulse width of rstout# 0: 1 ms 1: 25 ms 2: 125 ms 3: 5 sec
F81867 dec, 2011 v0.12p 95 watchdog timer configuration register 2 ? base address + 06h bit name r/w reset default description 7-0 wd_time r/w 5vsb 0 time of watchdog timer watchdog pme control register ? base address + 0ah bit name r/w reset default description 7 wdt_pme r 5vsb -- the pme status. this bit will set when wdt_pme_en is set and the watchdog timer is 1 unit before time out (or time out). 6 wdt_pme_en r/w 5vsb 0 0: disable watchdog pme. 1: enable watchdog pme. 5-1 reserved -- -- reserved. 0 wdout_en r/w 5vsb 0 0: disable watchdog time out output via wdtrst#. 1: enable watchdog time out output via wdtrst#. 6.8 acpi function the advanced configuration and power interface (a cpi) is a system for controlling the use of power in a computer. it lets computer manufacture r and user to determine the computer?s power usage dynamically. there are three acpi states that are of primar y concern to the system designer and they are designated s0, s3 and s5. s0 is a full-power state; the computer is being actively used in this state. the other two are called sleep states and reflect differ ent power consumption when power-down. s3 is a state that the processor is powered down but the last procedural state is being stored in memory which is still active. s5 is a state that memory is off and the last procedural state of the processor has been stored to the hard disk. take s3 and s5 as comparison, si nce memory is fast, the computer can quickly come back to full-power state, the disk is slower than the memory and the computer takes longer time to come back to full-power state. however, since the memory is off, s5 draws the minimal power comparing to s0 and s3. acpi includes three sub items as below: 1. power control (include wake up via sleep stat e, wake up stage detection, ac loss & resume control methods) 2. intel power saving function (deep sleep well, dsw: see next section for the detail) 3. eu power saving function (eup/erp command lot 6.0: see next section for the detail) where item 2 & 3 could be coexisted via erp_ ctrl0# (follow slp_sus#) & erp_ctrl1# (after the system enters s3 1.024s & s5 6. 4s, eup/erp mode could be achieved). before entering into the main section, let?s check out the related hardware control signal first.
F81867 dec, 2011 v0.12p 96 control signal power on/off control (ac resume) power management event wake up intel dsw hand shaking eup/erp control rsmrst# s3# s5# pwsin# pwsout# atxpg_in ps_on# pwok pme# ps/2 kb/ms ri1#/ri2# gpio0x/gpio1x slp_sus# sus_ack# sus_warn# erp_ctrl0# erp_ctrl1# : supported : wake up via erp : wake up via system 6.8.1 power control 6.8.1.1 wake up via sleep state when the system is at the normal sleep state (s3, s4, s5) or deep sleep (g3?) state, F81867 could wake up via pwsout# & pme#. see below for the related registers: : supported 6.8.1.2 wake up stage detection F81867 is counted on the chipset slp_s3#, slp_s4#/ slp_s5# stage, to decide the wake up stage as below: acpi stage slp_s3# slp_s4# /slp_s5# s0 h h s3 l h s5 l l wake up by pme# index 0x2d cr0a index 0xe0, 0xe8 cr0a index 0xf0~0xf3 normal sleep state eup/erp wake up by pwsout# index 0x2d cr 0a index 0x30 cr0a index 0xe0, 0xe8 cr0a index 0xf4 normal sleep state eup/erp
F81867 dec, 2011 v0.12p 97 h: high; l: low power saving mode would be activated via cr0a index e0 bit 7. 6.8.1.3 ac loss & resume control methods there are 4 modes under power loss state via setting acpi control register. the always on, always off, keep last state & bypass mode. in keep last state mode, one register will latch the status before power loss. if it is power on before power loss, it will automatica lly power on when power is resumed. if it is power off before power loss, it will remain power of f when power is resumed. see below for the detail: mode explanation always on (s0) when ac resume, the system will power on aut omatically (send a pw sout# low pulse and then sinking the ps_on# low). see below for the timing: vbat vsb rsmrst# s3# ps_on# psin# psout# vcc3v s0 s5 s0 s5 s5 always off (s5) when ac resume, the system is in off state and waiting for the wakeup events. see below for the timing: vbat vsb rsmrst# s3# ps_on# psin# psout# vcc3v user press the button g3 s0 s5 s0 s5 bypass (follow the when ac resume, inverting the s3 signal to ps_on#. see below for the timing:
F81867 dec, 2011 v0.12p 98 chipset after g3 stage) vbat vsb rsmrst# s3# ps_on# psin# psout# vcc3v s0 s5 s0 s5 s5 keep last state atxpg_in, vcc (pwok), vsb (rsmrst) and s3 signals to detect the sleep state while ac loss occur. one of the signal (atxpg_in or vcc under 2.8v or vsb under 2.8v) sinks low, sio will latch the s3 signal to decide the system to be at ?always on? or ?always off? mode. see below table: signal ac loss state atxpg vsb vcc ac resume ac loss in s0/s1 (s3=1) always on ac loss in s3/s4/s5 (s3=0) always off 6.8.2 intel power saving function deep sleep well (dsw) the F81867 supports intel cougar point (cpt) chipset timing for sandy bridge (sugar bay or huron river platform). there are 4 pins for cpt cont rol: sus_warn#, sus_ack# , slp_sus# and dpwrok. for entering the intel deep sleep well (dsw) state, the pch will assert sus_warn# (low level) and turn off 5vdual. after the level of 5vdual is lower than 1.05v, F81867 will assert sus_ack# to inform pch it is ready for entering dsw. finally, pch will ramp down the internal vccsus and assert slp_sus# to F81867. F81867 will turn off the 5vsb and 3vsb by erp_ctrl0# and enter the dsw state. to exit dsw state, pch will de-assert slp_sus# , turn on the sus rail fets and ramp up internal 1.05v vccsus. after the sus rails voltages are up, rsmrst# will be desserted and the pch will release sus_warn# so that the 5vdual will ramp up. because the dsw function is controlled by the f81 867 instead of controlled by the pch directly, there will be more wakeup events such as lan, kb/mouse, gpio0x, gpio1x, sio ri# wake up rather than the 3 wakeup events (rtc, power butt on and gpio27) for intel dsw.
F81867 dec, 2011 v0.12p 99 in order to achieve the lower po wer consumption, F81867 provides the erp_ctrl1# to turn off the v3a so that the system can ent er the fintek g3? state. the block diagram below shows how the conn ection and control method for F81867 and pch . fig 6-17 the register for setting this mode is at cr0a, index 0xec [7:6]. when choose intel dsw mode, erp_ctrl0#, & erp_ctrl1# would follow slp_sus# . when choose intel dsw + fintek g3? mode, erp_ctrl0# would follows slp_sus#, & erp_ctrl1# will enter fintek erp mode after entering dsw mode for 6.4s (default, the time is programmable). in sum, there are three blocks in this mode (please re fer to the application circuit for the hw schematic): a. dsw control block: a-1 slp_sus#: sio input pin from cpt pch slp_sus#. a-2 sus_warn#: sio input pin from cpt pch sus_warn#. a-3 sus_ack#: sio output pin to cpt pch susack#. a-4 dpwrok: sio output pin to cpt pch dpwrok. b. erp control block: b-1 erp_ctrl0#: support ?cpt pch dsw? control mode which is a low active signal to turn on/off 3vsb/5vsb power source by p mosfet. b-2 erp_ctrl1#: support ?fintek g3? ? control mode which is a low active signal to turn on/off 3va/5va power source by p mosfet. s0 state s3 state s4/s5 dsw g3? g3 atx power 5vsb vcc 5vdual 3.3v vsb vr v5a erp_ctrl0# (slp_sus_fet) 5vsb 3vsb v3a cpt pch F81867 sus_warn# sus_ack# slp_sus# 5va_pwok# rsmrst# v3a v5a 3vsb dpwrok rsmrst# 5vdual sus_warn# mb logic 5vdual control erp_ctrl1# sus_warn erp_ctrl0# erp_ctrl1# v detect & delay (invert from pch) suswarn# susack# i_3vsb 1.05v
F81867 dec, 2011 v0.12p 100 c. wake up event block: power button external lan pch internal lan ps2 kb/mouse sio ri# rtc gpio0x/1x v v x v x x v note: by pressing/triggering any of the above pin, the system could wake up from the sleep (s4/s5) dsw and g3? mode. v: supported. x: does not supported. 6.8.3 power saving controller (fintek erp mode) the two pins, erp_ctrl0# and erp_ctrl1#, which control the standby power rail on/off to fulfill the purpose which decreases the power consumption when the sy stem is in the sleep state or the soft-off state. these two pins connected to the external pmoss and t he defaults are high in the sleep state in order to cut off all the standby power rails to save the power consumption. if the system needs to support wake-up function, the two pins can be programmable to set which power rail to turn on. the programmable register is powered by the battery. so, the setting is kept even the ac power is lost when the register is set. at the power saving state (fintek calls it g3? state), the F81867 consumes 5vsb power rail only to realize a low power consumption system. the register for setting this mode is at cr0a, index 0xec [7:6]. when choose fintek g3? mode, erp_ctrl0# & erp_ctrl1# will enter s5. after entering s5 for 6.4s (default, the time is programmable), these two pins would send high level signal and then cu t off all the power sources except atx_5vsb (power consumption is about 15mw). in order to avoid the in rush current from atx_5vsb, F81867 also provide the soft start circuits at these two pins. see the related regi ster for the soft start circuit (cr0a, index 0xec [4]). in sum, there are two blocks in this mode (please refer to the application circuit for the hw schematic): a. eup control block: erp_ctrl0# and erp_ctrl1# are low active signals to turn on/off 5vsb power source by p mosfet. b. wake up event block via: power button external lan pch internal lan ps2 kb/mouse sio ri# rtc gpio0x/1x v v x v v x v note: by pressing/triggering any of the above pin, the system could wake up from the sleep (s4/s5) dsw and g3? mode. v: supported. x: does not supported.
F81867 dec, 2011 v0.12p 101 please see below for fintek g3? (erp) timing:
F81867 dec, 2011 v0.12p 102
F81867 dec, 2011 v0.12p 103
F81867 dec, 2011 v0.12p 104 6.8.4 acpi timing see below for the related acpi timing: 6.8.4.1 g3 to s0 atx_vsb v5a/v3a 5vsb/3vsb dual5v 5vcc/3vcc dpwrok slp_sus# rsmrst# sus_warn# sus_ack# pwsin# pwsout# s5# s3# ps_on# pwok erp_ctrl0# erp_ctrl1# fig 6-18
F81867 dec, 2011 v0.12p 105 6.8.4.2 g3 to s0 (only dsw) atx_vsb v5a/v3a 5vsb/3vsb dual5v 5vcc/3vcc dpwrok slp_sus# rsmrst# sus_warn# sus_ack# pwsin# pwsout# s5# s3# ps_on# pwok erp_ctrl0# erp_ctrl1# fig 6-19
F81867 dec, 2011 v0.12p 106 6.8.4.3 g3 to s0 (dsw & erp, ac resume green bold line) atx_vsb v5a/v3a 5vsb/3vsb dual5v 5vcc/3vcc dpwrok slp_sus# rsmrst# sus_warn# sus_ack# pwsin# pwsout# s5# s3# ps_on# pwok erp_ctrl0# erp_ctrl1# ac fig 6-20
F81867 dec, 2011 v0.12p 107 6.8.4.4 dsw to s0 atx_vsb v5a/v3a 5vsb/3vsb dual5v 5vcc/3vcc dpwrok slp_sus# rsmrst# sus_warn# sus_ack# pwsin# pwsout# s5# s3# ps_on# pwok erp_ctrl0# erp_ctrl1# fig 6-21
F81867 dec, 2011 v0.12p 108 6.8.4.5 s0 to dsw fig 6-22 atx_vsb v5a/v3a 5vsb/3vsb dual5v 5vcc/3vcc dpwrok slp_sus# rsmrst# sus_warn# sus_ack# pwsin# pwsout# s5# s3# ps_on# pwok erp_ctrl0# erp_ctrl1#
F81867 dec, 2011 v0.12p 109 6.8.4.6 s0 to g3? fig 6-23 z rsmrst# signal: powered by vbat sink low. z dpwrok/pwok signal: powered by vbat sink low. z 3vsb 2.8v/2.5v and gate slp_sus#/dpwrok for intel mode atx_vsb v5a/v3a 5vsb/3vsb dual5v 5vcc/3vcc dpwrok slp_sus# rsmrst# sus_warn# sus_ack# pwsin# pwsout# s5# s3# ps_on# pwok erp_ctrl0# erp_ctrl1#
F81867 dec, 2011 v0.12p 110 pwrok signals vdd3vok atxpwgd pwrok delay fig 6-24 pwrok is delayed 400ms (default) as vcc arrives 2.8v, and the delay timing can be programmed via register (100ms ~ 400ms). 6.9 uart the F81867 provides up to 6 uart ports and supports irq sharing for system application. they are compatible with 16c550/16c650/16c750 and 16c850 .the uarts are used to convert data between parallel format and serial format. they convert pa rallel data into serial format on transmission and serial format into parallel data on receiver side. the serial format is form ed by one start bit, followed by five to eight data bits, a parity bit if programmed and one ( 1.5 or 2 ) stop bits. the uarts include complete modem control capability and an interrupt system that may be software trailed to the computing time required to handle the communication link. they have fifo mode to reduc e the number of interrupts presented to the host. both receiver and transmitter have a 128-byte fifo. the uart control register control & define the asynchronous protocol data communications including data length, stop bit, parity & baud rate selection. the below content is about the uarts device register descriptions. all the registers are for software porting reference. receiver buffer register ? base + 0 bit name r/w reset default description 7-0 rbr r lreset# 00h the data received. read only when lcr [7] is 0 transmitter holding register ? base + 0 bit name r/w reset default description 7-0 thr w lreset# 00h data to be transmitted. write only when lcr [7] is 0 divisor latch (lsb) ? base + 0 bit name r/w reset default description 7-0 dll r/w lreset# 01h baud generator divisor low byte. access only when lcr [7] is 1.
F81867 dec, 2011 v0.12p 111 divisor latch (msb) ? base + 1 bit name r/w reset default description 7-0 dlm r/w lreset# 00h baud generator divisor high byte. access only when lcr [7] is 1. interrupt enable register (ier) ? base + 1 bit name r/w reset default description 7-5 reserved - - - reserved. 4 sm2 r/wc lreset# 0 this bit is used only in 9-bit mode and always returns ?0? when 9-bit mode is disabled. 0: the receiver could receive data byte. 1: the receiver could only receive address byte and issue an interrupt when the address is received. 3 edssi r/w lreset# 0 enable modem status interrupt. access only when lcr [7] is 0. 2 elsi r/w lreset# 0 enable line status error interrupt. access only when lcr [7] is 0. 1 etbfi r/w lreset# 0 enable transmitter holding register empty interrupt. access only when lcr [7] is 0. 0 erbfi r/w lreset# 0 enable received data available interrupt. access only when lcr [7] is 0. interrupt identification register (iir) ? base + 2 bit name r/w reset default description 7 fifo_en r lreset# 0 0: fifo is disabled 1: fifo is enabled. 6 fifo_en r lreset# 0 0: fifo is disabled 1: fifo is enabled. 5-4 reserved - lreset# - reserved. 3-1 irq_id r lreset# 00 000: interrupt is caused by modem status 001: interrupt is caused by transmitter holding register empty 010: interrupt is caused by received data available. 110: interrupt is caused by character timeout 011: interrupt is caused by line status. 0 irq_pendn r lreset# 1 1: interrupt is not pending. 0: interrupt is pending. fifo control register ? base + 2 bit name r/w reset default description 7-6 rcv_trig w lreset# 00 00: receiver fifo trigger level is 1. 01: receiver fifo trigger level is 4. 10: receiver fifo trigger level is 8. 11: receiver fifo trigger level is 14. 5-3 reserved - lreset# - reserved. 2 clrtx r lreset# 0 reset the transmitter fifo. 1 clrrx r lreset# 0 reset the receiver fifo. 0 fifo_en r lreset# 0 0: disable fifo. 1: enable fifo.
F81867 dec, 2011 v0.12p 112 line control register (lcr) ? base + 3 bit name r/w reset default description 7 dlab r/w lreset# 0 0: divisor latch can?t be accessed. 1: divisor latch can be accessed via base and base+1. 6 setbrk r/w lreset# 0 0: transmitter is in normal condition. 1: transmit a break condition. 5 stkpar r/w lreset# 0 xx0: parity bit is disable 001: parity bit is odd. 011: parity bit is even 101: parity bit is logic 1 111: parity bit is logic 0 4 eps r/w lreset# 0 3 pen r/w lreset# 0 2 stb r/w lreset# 0 0: stop bit is one bit 1: when word length is 5 bit stop bit is 1.5 bit else stop bit is 2 bit 1-0 wls r/w lreset# 00 00: word length is 5 bit 01: word length is 6 bit 10: word length is 7 bit 11: word length is 8 bit modem control register (mcr) ? base + 4 bit name r/w reset default description 7-5 reserved - lreset# - reserved. 4 loop r/w lreset# 0 0: uart in normal condition. 1: uart is internal loop back 3 out2 r/w lreset# 0 0: all interrupt is disabled. 1: interrupt is enabled (disabled) by ier. 2 out1 r/w lreset# 0 read from msr[6] while in loop back mode 1 rts r/w lreset# 0 0: rts# is forced to logic 1 1: rts# is forced to logic 0 0 dtr r/w lreset# 0 0: dtr# is forced to logic 1 1: dtr# is forced to logic 0 line status register (lsr) ? base + 5 bit name r/w reset default description 7 rcr_err r lreset# 0 0: no error in the fifo when fifo is enabled 1: error in the fifo when fifo is enabled. 6 temt r lreset# 1 0: transmitter is in transmitting. 1: transmitter is empty. 5 thre r lreset# 1 0: transmitter holding register is not empty. 1: transmitter holding register is empty. 4 bi r lreset# 0 0: no break condition detected. 1: a break condition is detected. 3 fe r lreset# 0 0: data received has no frame error. 1: data received has frame error. 2 pe r lreset# 0 0: data received has no parity error. 1: data received has parity error. 1 oe r lreset# 0 0: no overrun condition occurred. 1: an overrun condition occurred. 0 dr r lreset# 0 0: no data is ready for read. 1: data is received.
F81867 dec, 2011 v0.12p 113 modem status register (msr) ? base + 6 bit name r/w reset default description 7 dcd r - - complement of dcd# input. in loop back mo de, this bit is equivalent to out2 in mcr. 6 ri r - - complement of ri# input. in loop back mode , this bit is equivalent to out1 in mcr 5 dsr r - - complement of dsr# input. in loop back mode , this bit is equivalent to dtr in mcr 4 cts r - - complement of cts# input. in loop back mode , this bit is equivalent to rts in mcr 3 ddcd r lreset# 0 0: no state changed at dcd#. 1: state changed at dcd#. 2 teri r lreset# 0 0: no trailing edge at ri#. 1: a low to high transition at ri#. 1 ddsr r lreset# 1 0: no state changed at dsr#. 1: state changed at dsr#. 0 dcts r lreset# 1 0: no state changed at cts#. 1: state changed at cts#. scratch register ? base + 7 bit name r/w reset default description 7-0 scr r/w lreset# 00h scratch register.
F81867 dec, 2011 v0.12p 114 programmable baud rate the below table shows the use of baud generator with the different frequency 1.8461 mhz, 14.769 mhz, 24mhz: 16 * divisor com_clk = baudrate fig 6-25 6.10 amd tsi and intel peci 3.0 functions the F81867 provides intel peci/amd tsi interfaces for new generational cpu temperature sensing. in amd tsi interface, there are sic and sid signals for temperature information reading from amd cpu. the sic signal is for clocking use, the other is for data transferring. more detail, please refer register description.
F81867 dec, 2011 v0.12p 115 scl vddio amd cpu sic sid 300 300 sda sio fig 6-26 amd tsi in intel peci interface, the F81867 can connect to the cpu directly. the F81867 can read the temperature data from cpu, then the fan control machine of F81867 can implement the fan to cool down the cpu temperature. the application circuit is as below. peci sio cpu peci intel 100 avoid pre-bios floating fig 6-27 intel peci please see below for the intel peci 3.0 spec. commands. the F81867 integrated most of those commands for the future advantage application. more detail, please refer to the register descriptions. F81867 support peci 3.0 command name peci 1.0 command name status v ping( ) ping( ) v gettemp( ) get t emp( ) v getdib( ) v rdiamsr( ) - wriamsr( ) - rdpciconfiglocal( ) not available in mobile/dt - wrpciconfiglocal( ) not available in mobile/dt - rdpciconfig( ) not available in mobile/dt - wrpciconfig( ) not available in mobile/dt v rdpkgconfig( ) v wrpkgconfig( ) fig 6-28
F81867 dec, 2011 v0.12p 116 6.11 over voltage protection F81867 over voltage protection function could protect the damage from voltage spikes via over voltage protection (ovp) function. voltage protection function is enabled via setting the related register. when the force mode occurs, the system would shut down and then can not boot at all. only re-plugging the power code (cut off vsb) could re-activate or re-boot the system at the force mode. 6.12 microcontroller a microcontroller contains a processor core, memory , and programmable input/output peripherals made it economical for designers. basically microcontrollers are designed for embedded applications such as automobile engine control systems, medical devices, re mote controls, office machines, appliances, power tools, and toys. F81867 integrates 8 bit 8032 embedded microcontroller which could access gpio, pwm, hardware monitor, kbc, acpi & cir function. see detail for the c side regeister. 6.13 debug port function the debug port is the interface for host to cont rol the ec side devices. when it is enabled, it replaces ec to control its peripherals an d could also access sfr and internal ram of c. please refer to the debug port register in ec side to fully control the ec. debug port data register ? offset 00h bit name r/w reset default description 7-0 dbport_data r/w 5vsb 0h write data to this byte will change the ec side register which address is set by dbport_ec_addr. read data from this byte will return the value of ec side register which address is set by dbport_ec_addr. debug port control register ? offset 01h bit name r/w reset default description 7 brk_ptr_trig r 5vsb 0 this bit is set when a break point is triggered. 6-1 reserved - - - reserved. 7-0 dbport_en r/w 5vsb 0 0: disable debug port. 1: enable debug port.
F81867 dec, 2011 v0.12p 117 debug port ec address low byte ? offset 04h bit name r/w reset default description 7-0 dbport_ec_addr r 5vsb 0 this is the low byte of ec peripheral address. debug port ec address high byte ? offset 05h bit name r/w reset default description 7-0 dbport_ec_addr r 5vsb 0 this is the high byte of ec peripheral address. 6.14 h2e function h2e is the interface for host to ec. host could use this register to notify the ec what to do and can get information return from ec. some registers are pre-definition. user coul d change their definition for custom use. h2e control register ? offset 00h bit name r/w reset default description 7 p80_dec_range r/w 5vsb 0 this bit is used to select the 0x80 port (the address could be set by ec) decode range. 0: decode 0x80 only. 1: decode 0x80 and 0x81. 6 e2h_int_en r/w 5vsb 0 0: disable ec assert s interrupt to host. 1: enable ec asserts interrupt to host. 5 e2h_data_avail r 5vsb 0 this bit is set when ec write data to e2h_data (offset + 02h) and is auto clear when host read e2h_data. 4 h2e_data_avail r 5vsb 0 this bit is set when hostwrite data to h2e_data (offset + 01h) and is auto clear when ec read h2e_data. 3-2 e2h_data_type r 5vsb 0 this byte is pre-definition for the ty pe of e2h_data. user could change its usage corresponding to their implementat ion. for the pre-definition function, host read the type to determine the meaning of e2h_data. 1-0 h2e_data_type r 5vsb 0 this byte is pre-definition for the ty pe of h2e_data. user could change its usage corresponding to their implementat ion. for the pre-definition function, host read the type to determine the meaning of h2e_data. h2e data register ? offset 01h bit name r/w reset default description 7-0 h2e_data r/w 5vsb 0 host to ec data. e2h data register ? offset 02h bit name r/w reset default description 7-0 e2h_data r 5vsb 0 this byte is written by ec. host could read this byte to get the information return from ec.
F81867 dec, 2011 v0.12p 118 wdt control port ? offset 03h bit name r/w reset default description 7 p80_wdt_to_st r/w 5vsb 0 the bit is pre-defined for port 80 wdt function. user could change its usage. the wdt is implemented by firmware. w hen time out occurs, ec set this bit and could assert reset signal from defined pins. host read this bit to check the status and write ?1? to clear status. 6 p80_wdt_en r/w 5vsb 0 the bit is pre-defined for port 80 wdt function. ec read this bit to enable/disable wdt function. 0: disable wdt function. 1: enable wdt function. 5-4 p80_wdt_unit r/w 5vsb 0 the bit is pre-defined for port 80 wdt function. ec read this bit to decide wdt unit. the unit is user defined. 3-0 p80_wdt_pin r/w 5vsb 0 the bit is pre-defined for port 80 wdt function. this is the mask for wdt event pins. the pin to assert wdt event is user defined. wdt time register ? offset 04h bit name r/w reset default description 7-0 p80_wdt_time r/w 5vsb ffh the byte is pre-defined for port 80 wdt function. host writes this byte to inform ec the wdt count down time. wdt enable code ? offset 05h bit name r/w reset default description 7-0 p80_wdt_code r/w 5vsb - the byte is pre-defined for port 80 wdt function. ec wait for wdt start until 0x80 port data matches this byte. 80 port data ? offset 06h bit name r/w reset default description 7-0 p80_data r/w 5vsb - the data write to 0x80/0x81(if p80_dec_range is set) will be latched into this byte. ec could dump the value into internal ram for further use. 80 port data ? offset 07h bit name r/w reset default description 7-0 p80_last_data r 5vsb - this byte is pre-defined for the last 0x 80 port last data. ec write 0x80 port data back to this byte.
F81867 dec, 2011 v0.12p 119 7. register description the configuration register is used to control the behavior of the corresp onding devices. to configure the register, using the index port to select the index and then writing da ta port to alter the parameters. the default index port and data port are 0x4e and 0x4f respectively. pull down the rts1# pin to change the default value to 0x2e/0x2f. to enable configuration, the entry key 0x87 mu st be written to the index port. to disabl e configuration, write exit key 0xaa to the index port. following is an example to enable c onfiguration and disable configuration by using debug. -o 4e 87 -o 4e 87 ( enable configuration ) -o 4e aa ( disable configuration ) the following is a register map (total devices) grouped in hexadecimal address order, which shows a summary of all registers and their default value. please refer to eac h device chapter if you want more detail information. global control registers ?-? reserved or tri-state global control registers register 0x[hex] register name default value msb lsb 02 software reset register - - - - - - - 0 07 logic device number register (ldn) 0 0 0 0 0 0 0 0 20* chip id register 0 0 0 1 0 0 0 0 21* chip id register 0 0 0 1 0 0 0 0 23* vendor id register 0 0 0 1 1 0 0 1 24* vendor id register 0 0 1 1 0 1 0 0 25* i2c address register 0 0 0 0 0 0 0 0 26* clock select register 0 0 - 0 0 0 1 1 27* port select register 1/0 1/0 0 1/0 0 0 - 0 28* multi function select 1 register - 1 1 0 0 0 0 0 28* multi function select 2 register 0 0 0 0 0 0 0 0 29* multi function select 3 register 0 0 0 0 0 0 1 1 29* 10hz clock divisor high byte 0 0 0 0 0 0 1 1 2a* 10hz clock divisor low byte 1 1 1 0 0 1 1 1 2b* multi function select 4 register 0 0 0 - - - 1 0 2b* 10hz fine tune clock count high byte - - - - - - - - 2c* 10hz fine tune clock count low byte - - - - - - - - 2c* gpio0 enable register - - - 0 0 0 0 0
F81867 dec, 2011 v0.12p 120 2c* gpio1 enable register 0 0 0 - 1 1 1 1 2c* gpio2 enable register 0 0 0 0 0 0 0 0 2c* c port enable register 1 1 1 0 0 0 0 0 2d* wakeup control register - - - - 1 0 0 0 *aceess by c and host. 7.1 global control registers 7.1.1 software reset register ? index 02h bit name r/w reset default description 7-1 reserved - - - reserved 0 soft_rst r/w - 0 write 1 to reset the register and device powered by vdd (vcc). 7.1.2 logic device number register (ldn) ? index 07h bit name r/w reset default description 7-0 ldn r/w lreset# 00h 00h: select fdc device c onfiguration registers. 03h: select parallel port devic e configuration registers. 04h: select hardware monitor device configuration registers. 05h: select kbc device c onfiguration registers. 06h: select gpio device c onfiguration registers. 07h: select wdt device configuration registers. 0ah: select pme, acpi and erp dev ice configuration registers. 0eh: select h2e device co nfiguration registers. 10h: select uart1 device co nfiguration registers. 11h: select uart2 device configuration registers. 12h: select uart3 device co nfiguration registers. 13h: select uart4 device co nfiguration registers. 14h: select uart5 device co nfiguration registers. 15h: select uart6 device co nfiguration registers. otherwise: reserved. 7.1.3 chip id register ? index 20h bit name r/w reset default description 7-0 chip_id1 r - 10h chip id 1. 7.1.4 chip id register ? index 21h bit name r/w reset default description 7-0 chip_id2 r - 10h chip id2. 7.1.5 vendor id register ? index 23h bit name r/w reset default description 7-0 vendor_id1 r - 19h vendor id 1.
F81867 dec, 2011 v0.12p 121 7.1.6 vendor id register ? index 24h bit name r/w reset default description 7-0 vendor_id2 r - 34h vendor id 2. 7.1.7 i2c address select register ? index 25h bit name r/w reset default description 7-1 i2c_addr r/w 5vsb 0 i2c address is used to r/w hardware monitor registers. the default address is determined by i2c_addr power on strap pin. it could also be changed by writing this byte with the entry key 0x19, 0x34. the default value is 0x2e which indicates the address is 0x5c. 0 en_ara_mode r/w 5vsb 0 0: disable i2c ara. 1: enable i2c ara. 7.1.8 clock select register ? index 26h bit name r/w reset default description 7-6 clk_sel r/w 5vsb 0 the clock source of clkin. 00: clkin is 48mhz 10: clkin is 24mhz 01: clkin is 14.318mhz. 10: reserved. 5 reserved - - reserved. 4 mo_pin_lvl_sel r/w 5vsb 0 mclk/mdata input level select. 0: ttl level. 1: low level with 0.6v low and 0.9v high. 3 pin76_lvl_sel r/w 5vsb 0 pin 76 input level select. 0: ttl level. 1: low level with 0.6v low and 0.9v high. 2 pin71_lvl_sel r/w 5vsb 0 pin 71 input level select. 0: ttl level. 1: low level with 0.6v low and 0.9v high. 1 pin68_lvl_sel r/w 5vsb 1 pin 68 input level select. 0: ttl level. 1: low level with 0.6v low and 0.9v high. 0 pin67_lvl_sel r/w 5vsb 1 pin 67 input level select. 0: ttl level. 1: low level with 0.6v low and 0.9v high.
F81867 dec, 2011 v0.12p 122 7.1.9 port select register ? index 27h bit name r/w reset default description 7 ovp_mode r/w vbat* - 0: enable ovp function. 1: default is disabled; internal pull high 47k . the default value is determined by power on strap. 6 at_mode r/w 5vsb - 0: atx mode. 1: at mode. the default value is determined by power on strap. 5 gpio_dec_range r/w 3vcc 0 0: the gpio i/o space is 8-byte. 1: the gpio i/o space is 16-byte. 4 port_4e_en r/w 5vsb* - 0: the configuration register port is 2e/2f. 1: the configuration register port is 4e/4f. this register is power on trapped by rts1#/ config4e_2e. pull down to select port 2e/2f. this bit is accessed by the host side only. 3-2 gpio_prog_sel r/w 5vsb 0 index 0x2c register select. 00: gpio0_en 01: gpio1_en 10: gpio2_en 11: c_port_en. 1 host_stop_ c r/w - 0 host set this bit ?1? to stop c. to enter debug mode, host should stop this bit first. this bit is accessed by host side only. 0 clk_tune_prog_ en r/w 3vcc 0 set ?1? to enable index 0x29, 0x2a, 0x2b, 0x2c function as clock fine tune register. 7.1.10 multi-function select 1 register ? index 28h (available when gpio_prog_sel[0] = 0) bit name r/w reset default description 7 reserved - - - reserved 6 fdc_gp_en r/w 5vsb 1 pin 9 ~ 21 function select. these pins are controlled by fdc_gp_en, uart5_func_sel, and uart6_func_sel. if all these bits are clear to ?0?, the function would be fdc. 5 lpt_gp_en r/w 5vsb 1 pin 102 ~ 118 function select. 0: functions as parallel port. 1: functions as gpio7x/gpio8x. 4 mo_ i2c _en r/w 5vsb 0 pin 61, 62 function select. 0: ps/2 mouse interface mclk/mdata. 1: i2c scl/sda. 3-2 uart5_func_sel r/w 5vsb 0 uart 5 function select. 00: no uart 5 pin. 01: simple uart, only sin5 and sout5 are available. pin 57 will be function as sout5 and pin 58 will be function as sin5. 10: simple uart with rts#. pin 59 will be function as rts5#. 11: full uart, pin 57 ~ 59, 17 ~ 21 will function as uart 5 pins.
F81867 dec, 2011 v0.12p 123 1-0 uart6_func_sel r/w 5vsb 0 uart6 function select. 00: no uart6 pin. 01: simple uart, only sin6 and sout6 are available. pin 10 will be function as sout6 and pin 11 will be function as sin6. 10: simple uart with rts#. pin 9 will be function as rts6#. 11: full uart, pin 9 ~ 16 will function as uart 6 pins. 7.1.11 multi-function select 2 register ? index 28h (a vailable when gpio_prog_sel[0] = 1 ) bit name r/w reset default description 7 reserved - - - reserved 6 c_p32_pin59_en r/w vbat 0 0: disable c p32 from pin 59. 1: enable c p32 from pin59. 5 c_p31_pin57_en r/w vbat 0 0: disable c p31 from pin 57. 1: enable c p31 from pin57. 4 c_p30_pin58_en r/w vbat 0 0: disable c p30 from pin 58. 1: enable c p30 from pin58. 3-2 reserved - - - reserved 1 cir_pin76_en r/w vbat 0 0: disable cirrx# from pin76. the pin function is alert#/gpio20/scl/cirrx#. 1: enable cirrx# from pin76. 0 cir_pin71_en r/w vbat 0 0: disable cirrx# from pin71. the pin function is beep/gpio16/sda/cirrx#. 1: enable cirrx# from pin71. 7.1.12 multi function select 3 register ? index 29h (available when clk_ tune_prog_en = 0) bit name r/w reset default description 7-6 uart4_func_sel r/w 5vsb 0 uart4 function select. 00: no uart4 pin. pin 44 ~ 51 are all gpios. 01: simple uart, only sin4 and sout4 ar e available. pin 50 will be function as sout4 and pin 51 will be function as sin4. 10: simple uart with rts# function only. pin 48 will be function as rts4#. 11: full uart, pin 44 ~ 51 will be function as uart pins. 5-4 uart3_func_sel r/w 5vsb 0 uart3 function select. 00: no uart3 pin. pin 36 ~ 43 are all gpios. 01: simple uart, only sin3 and sout3 ar e available. pin 42 will be function as sout3 and pin 43 will be function as sin3. 10: simple uart with rts# function only. pin 40 will be function as rts3#. 11: full uart, pin 36 ~ 43 will be function as uart pins. 3 scl3_pin76_en r/w 5vsb 0 0: disable scl from pin 76. 1: enable scl from pin 76. there is only one slave in the current design, it is recommended to select only one pin for scl. when multi pins are sele cted, the priority of these bits is mo_i2c_en > scl_pin76_en > scl_pin67_en.
F81867 dec, 2011 v0.12p 124 2 sda3_pin71_en r/w 5vsb 0 0: disable sda from pin 76. 1: enable sda from pin 76. there is only one slave in the current design, it is recommended to select only one pin for sda. when multi pins are sele cted, the priority of these bits is mo_i2c_en > sda_pin7 1_en > sda_pin68_en. 1 sda2_pin68_en r/w 5vsb 1 0: disable sda from pin 68. 1: enable sda from pin 68. there is only one slave in the current design, it is recommended to select only one pin for sda. when multi pins are sele cted, the priority of these bits is mo_i2c_en > sda_pin7 1_en > sda_pin68_en. 0 scl2_pin67_en r/w 5vsb 1 0: disable scl from pin 67. 1: enable scl from pin 67. there is only one slave in the current design, it is recommended to select only one pin for scl. when multi pins are sele cted, the priority of these bits is mo_i2c_en > scl_pin76_en > scl_pin67_en. 7.1.13 10hz clock divisor high byte ? index 29h (available when clk_ tune_prog_en = 1) bit name r/w reset default description 7 fine_tune_start w - - write ?1? to start the fine tune mechanis m. the hardware will start to count 10 cycle internal 500khz clock with 48mhz clock. the count will present in index 0x2a, 0x2b. 6-4 reserved - - - reserved. 3-0 clk10hz_div r/w vbat 4?h3 the divisor of 10hz clock. internal 10hz clock is used to generate wdt event. it is divided from 10khz clock and could be fine tune by change its divisor. 7.1.14 10hz clock divisor low byte ? index 2ah (available when clk_ tune_prog_en = 0) bit name r/w reset default description 7 pwm3_lpt_pin_en r/w 5vsb 0 0: disable pwm3 from pin 110. 1: enable pwm3 from pin 110. 6 pwm2_lpt_pin_en r/w 5vsb 0 0: disable pwm2 from pin 109. 1: enable pwm2 from pin 109. 5 pwm1_lpt_pin_en r/w 5vsb 0 0: disable pwm1 from pin 108. 1: enable pwm1 from pin 108. 4 pwm0_lpt_pin_en r/w 5vsb 0 0: disable pwm0 from pin 107. 1: enable pwm0 from pin 107. 3 pwm3_pin_en r/w 5vsb 0 0: disable pwm3 from pin 20. 1: enable pwm3 from pin 20. 2 pwm2_pin_en r/w 5vsb 0 0: disable pwm2 from pin 19. 1: enable pwm2 from pin 19. 1 pwm1_pin_en r/w 5vsb 0 0: disable pwm1 from pin 18. 1: enable pwm1 from pin 18. 0 pwm0_pin_en r/w 5vsb 0 0: disable pwm0 from pin 17. 1: enable pwm0 from pin 17.
F81867 dec, 2011 v0.12p 125 7.1.15 10hz clock divisor low byte ? index 2ah (available when clk_tune_prog_en = 1) bit name r/w reset default description 7-0 clk10hz_div r/w vbat 8?he7 the divisor of 10hz clock. internal 10hz clock is used to generate wdt event. it is divided from 10khz clock and could be fine tune by change its divisor. 7.1.16 multi function select 4 register ? index 2bh (available when clk_ tune_prog_en = 0) bit name r/w reset default description 7 gpio67_en r/w vbat 0 pin 87 function select 0: pin 87 functions as s5#. 1: pin 87 functions as gpio67. 6 gpio66_en r/w vbat 0 pin 86 function select 0: pin 86 functions as dpwrok. 1: pin 86 functions as gpio66. 5 gpio65_en r/w vbat 0 pin 74 function select 0: pin 74 functions as pme#. 1: pin 74 functions as gpio65. 4-2 reserved - - - reserved 1 fanin3_en r/w vbat 1 pin 102 function select 0: pin 102 functions as sclt. 1: pin 102 functions as fanin3. 0 fanctrl3_en r/w vbat 0 pin 103 function select. 0: pin 103 functions as gpio70/pe. 1: pin 103 functions as fanctrl3. 7.1.17 10hz clock fine tune count high byte ? index 2bh (available when clk_ tune_prog_en = 1) bit name r/w reset default description 7 fine_tune_st - 5vsb - this bit indicates the fine tune mechanism is in process. 6-4 reserved - - - reserved 3-0 fine_tune_cnt r/w 5vsb 4?h3 this is the count of 10 cycles of internal 500khz clock with 48mhz clock. 7.1.18 10hz clock fine tune count low byte ? index 2ch (available when clk_ tune_prog_en = 1) bit name r/w reset default description 7-0 fine_tune_cnt r/w 5vsb 4?h3 this is the count of 10 cycles of internal 500khz clock with 48mhz clock.
F81867 dec, 2011 v0.12p 126 7.1.19 gpio0 enable register ? index 2ch (available when clk_ tune_prog_en = 0 and gpio_prog_sel = 2?b00) bit name r/w reset default description 7-5 reserved - - - reserved 4 gpio04_en r/w vbat 0 pin 56 function select. 0: pin 56 functions as slp_sus#. 1: pin 56 functions as gpio04. 3 gpio03_en r/w vbat 0 pin 55 function select. 0: pin 55 functions as sus_ack#. 1: pin 55 functions as gpio03. 2 gpio02_en r/w vbat 0 pin 54 function select. 0: pin 54 functions as sus_warn#. 1: pin 54 functions as gpio02. 1 gpio01_en r/w vbat 0 pin 53 function select. 0: pin 53 functions as erp_ctrl1#. 1: pin 53 functions as gpio01. 0 gpio00_en r/w vbat 0 pin 52 function select. 0: pin 52 functions as erp_ctrl0#. 1: pin 52 functions as gpio00. 7.1.20 gpio1 enable register ? index 2ch (available when clk_ gpio_prog_sel prog_en = 0 and gpio_prog_sel = 2?b01) bit name r/w reset default description 7 gpio17_en r/w vbat 0 pin 72 function select. 0: pin 72 functions as peci. 1: pin 72 functions as gpio17. 6 gpio16_en r/w vbat 0 pin 71 function select. 0: pin 71 functions as beep. 1: pin 71 functions as gpio16. 5 gpio15_en r/w vbat 0 pin 70 function select. 0: pin 70 functions as wdtrst#. 1: pin 70 functions as gpio15. 4 reserved - - - reserved 3 gpio13_en r/w vbat 1 pin 68 function select. 0: pin 68 functions as irrx. 1: pin 68 functions as gpio13. if sda_pin68_en is set, pin 68 will be function as sda. 2 gpio12_en r/w vbat 1 pin 67 function select. 0: pin 67 functions as irtx. 1: pin 67 functions as gpio12. if scl_pin67_en is set, pin 67 will be function as scl.
F81867 dec, 2011 v0.12p 127 1 gpio11_en r/w vbat 1 pin 66 function select. 0: pin 66 functions as led_vcc. 1: pin 66 functions as gpio11. 0 gpio10_en r/w vbat 1 pin 65 function select. 0: pin 65 functions as led_vsb. 1: pin 65 functions as gpio10. 7.1.21 gpio2 enable register ? index 2ch (available when clk_ tune_prog_en = 0 and gpio_prog_sel = 2?b10) bit name r/w reset default description 7 gpio27_en r/w vbat 0 pin 83 function select. 0: pin 83 functions as rsmrst#. 1: pin 83 functions as gpio27. 6 gpio26_en r/w vbat 0 pin 82 function select. 0: pin 82 functions as pwrok. 1: pin 82 functions as gpio26. 5 gpio25_en r/w vbat 0 pin 81 function select. 0: pin 81 functions as pson#. 1: pin 81 functions as gpio25. 4 gpio24_en r/w vbat 0 pin 80 function select. 0: pin 81 functions as s3#. 1: pin 81 functions as gpio24. 3 gpio23_en r/w vbat 0 pin 79 function select. 0: pin 68 functions as pwsout#. 1: pin 68 functions as gpio23. 2 gpio22_en r/w vbat 0 pin 78 function select. 0: pin 78 functions as pwsin#. 1: pin 78 functions as gpio22. 1 gpio21_en r/w vbat 0 pin 77 function select. 0: pin 77 functions as atxpg_in. 1: pin 77 functions as gpio21. 0 gpio20_en r/w vbat 0 pin 76 function select. 0: pin 76 functions as alert#. 1: pin 76 functions as gpio20. pin 76 will be function as scl: if scl_pin76_en is set. 7.1.22 c port enable register ? index 2ch (available when clk_tune_prog_en = 0 and gpio_prog_sel = 2?b11) bit name r/w reset default description 7 c_t2ex_en r/w vbat 0 set ?1? to enable c t2ex function from pin 16. 6 c_t2_en r/w vbat 0 set ?1? to enable c t2 function from pin 15. 5 c_p35_en r/w vbat 0 set ?1? to enable c p3.5 (also function as c t1) function from pin 14.
F81867 dec, 2011 v0.12p 128 4 c_p34_en r/w vbat 0 set ?1? to enable c p3.4 (also function as c t0) function from pin 13. 3 c_p33_en r/w vbat 0 set ?1? to enable c p3.3 (also function as c int1#) function from pin 12. 2 c_p32_en r/w vbat 0 set ?1? to enable c p3.2 (also function as c int0#) function from pin 9. 1 c_p31_en r/w vbat 0 set ?1? to enable c p3.1 (also function as c txd) function from pin 11. 0 c_p30_en r/w vbat 0 set ?1? to enable c p3.0 (also function as c rxd) function from pin 10. 7.1.23 wakeup control register ? index 2dh bit name r/w reset default description 7-4 reserved - - - reserved 3 wakeup_en r/w vbat 1 0: disable kb/mouse wakeup function. 1: enable kb/mouse wakeup function. 2-1 key_sel r/w vbat 00 select the keyboard wakeup key. accompany with key_sel_add, there are several key select as list key_sel_add key_sel wake key 0 00 ctrl + esc 0 01 ctrl + f1 0 10 ctrl + space 0 11 any key 1 00 windows wakeup key 1 01 windows power key 1 10 ctrl + alt + backspace 1 11 ctrl + alt + delete 0 mo_sel r/w vbat 0 select the mouse wakeup key. 0: wakeup by mouse clicking. 1: wakeup by mouse clicking or movement. 7.2 multifunction function register mapping table 7.2.1 multi function register mapping for fdc pin no. pin full name pin select configure register pin9 gpio50/densel#/rts6# densel index 27h bit3-2 = 00 index 28h bit6 and bit3-0 = 0 index 27h bit0 = 0 index 2ah bit3-0 = 0 pin10 gpio51/moa#/sin6 moa# pin11 gpio52/drva#/sout6 drva# pin12 gpio53/wdata#/dcd6# wdata# pin13 gpio54/dir#/ri6# dir# pin14 gpio55/step#/cts6# step# pin15 gpio56/hdsel#/dtr6 hdsel# pin16 gpio57/wgate#/dsr6# wgate# pin17 gpio60/rdata#/dcd5# rdata#
F81867 dec, 2011 v0.12p 129 pin18 gpio61/trk0#/ri5# trk0# pin19 gpio62/index#/cts5# index# pin20 gpio63/wpt#/dtr5# wpt# pin21 gpio64/dskchg#/dsr5# dskchg# 7.2.2 multi function register mapping for parallel port (lpt) pin no. pin full name pin select configure register pin102 fanin3/slct slct index 27h bit3-2 = 00 and bit0 = 0 index 28h bit5 = 0 index 2bh bit1-0 = 00 pin103 gpio70/pe/fanctl3/pwm_d ac3 pe pin104 gpio71/busy busy pin105 gpio72/ack# ack# pin106 gpio73/slin# slin# pin107 gpio74/init# init# pin108 gpio75/err# err# pin109 gpio76/afd# afd# pin110 gpio77/stb# stb# pin111 gpio80/pd0 pd0 pin112 gpio81/pd1 pd1 pin113 gpio82/pd2 pd2 pin114 gpio83/pd3 pd3 pin115 gpio84/pd4 pd4 pin116 gpio85/pd5 pd5 pin117 gpio86/pd6 pd6 pin118 gpio87/pd7 pd7 7.2.3 multi function register mapping for hardware monitor pin no. pin full name pin select configure register pin71 beep/gpio16/sda/cirrx# beep index 27h bit3-2 = 01 and bit0 = 0 index 29h bit2 = 0 index 2ch bit6 = 0 pin76 alert#/gpio20/scl/cirrx# alert# index 27h bit3-2 = 10 and bit0 = 0 index 29h bit3 = 0 index 2ch bit0 = 0 pin102 fanin3/slct fanin3 index 27h bit0 = 0 index 2bh bit1 = 1
F81867 dec, 2011 v0.12p 130 pin103 gpio70/pe/fanctl3/pwm_d ac3 fanctl3 index 27h bit0 = 0 index 2bh bit0 = 1 7.2.4 multi function register mapping for kbc (ps/2 mouse) pin no. pin full name pin select configure register pin61 mdata/scl mdata index 27h bit3-2 = 00 index 28h bit4 = 0 pin62 mclk/sda mclk 7.2.5 multi function register mapping for gpio0x pin no. pin full name pin select configure register pin52 erp_ctrl0#/gpio00 gpio00 index 27h bit3-2 = 00 and bit0 = 0 index 2ch bit0 = 1 pin53 erp_ctrl1#/gpio01 gpio01 index 27h bit3-2 = 00 and bit0 = 0 index 2ch bit1 = 1 pin54 sus_warn#/gpio02 gpio02 index 27h bit3-2 = 00 and bit0 = 0 index 2ch bit2 = 1 pin55 sus_ack#/gpio03 gpio03 index 27h bit3-2 = 00 and bit0 = 0 index 2ch bit3 = 1 pin56 slp_sus#/gpio04 gpio04 index 27h bit3-2 = 00 and bit0 = 0 index 2ch bit4 = 1 pin57 pin58 pin59 gpio05/sout5 gpio06/sin5 gpio07/rts5# gpio05 gpio06 gpio07 index 27h bit3-2 = 00 index 28h bit3-2 = 00 7.2.6 multi function register mapping for gpio1x pin no. pin full name pin select configure register pin65 gpio10/led_vsb gpio10 index 27h bit3-2 = 01 and bit0 = 0 index 2ch bit0 = 1 pin66 gpio11/led_vcc gpio11 index 27h bit3-2 = 01 and bit0 = 0 index 2ch bit1 = 1 pin67 scl/gpio12/irtx gpio12 index 27h bit3-2 = 01 and bit0 = 0 index 29h bit0 = 0 index 2ch bit2 = 1 pin68 sda/gpio13/irrx gpio13 index 27h bit3-2 = 01 and bit0 = 0 index 29h bit1 = 0 index 2ch bit3 = 1 pin69 gpio14/atx_at_trap gpio14 single function
F81867 dec, 2011 v0.12p 131 pin70 wdtrst#/gpio15 gpio15 index 27h bit3-2 = 01 and bit0 = 0 index 2ch bit5 = 1 pin71 beep/gpio16/sda/cirrx# gpio16 index 27h bit3-2 = 01 and bit0 = 0 index 29h bit2 = 0 index 2ch bit6 = 1 pin72 peci/gpio17 gpio17 index 27h bit3-2 = 01 and bit0 = 0 index 2ch bit7 = 1 7.2.7 multi function register mapping for gpio2x pin no. pin full name pin select configure register pin76 alert#/gpio20/scl/cirrx# gpio20 index 27h bit3-2 = 10 and bit0 = 0 index 29h bit3 = 0 index 2ch bit0 = 1 pin77 atxpg_in/gpio21 gpio21 index 27h bit3-2 = 10 and bit0 = 0 index 2ch bit1 = 1 pin78 pwsin#/gpio22 gpio22 index 27h bit3-2 = 10 and bit0 = 0 index 2ch bit2 = 1 pin79 pwsout#/gpio23 gpio23 index 27h bit3-2 = 10 and bit0 = 0 index 2ch bit3 = 1 pin80 s3#/gpio24 gpio24 index 27h bit3-2 = 10 and bit0 = 0 index 2ch bit4 =1 pin81 ps_on#/gpio25 gpio25 index 27h bit3-2 = 10 and bit0 = 0 index 2ch bit5 = 1 pin82 pwok/gpio26 gpio26 index 27h bit3-2 = 10 and bit0 = 0 index 2ch bit6 = 1 pin83 rsmrst#/gpio27 gpio27 index 27h bit3-2 = 10 and bit0 = 0 index 2ch bit7 = 1 7.2.8 multi function register mapping for gpio3x pin no. pin full name pin select configure register pin36 dcd3#/gpio30 gpio30 index 27h bit0 = 0 index 29h bit5-4 = 00 pin37 ri3#/gpio31 gpio31 pin38 cts3#/gpio32 gpio32 pin39 dtr3#/gpio33 gpio33 pin40 rts3#/gpio34 gpio34 pin41 dsr3#/gpio35 gpio35 pin42 sout3/gpio36 gpio36
F81867 dec, 2011 v0.12p 132 pin43 sin3/gpio37 gpio37 7.2.9 multi function register mapping for gpio4x pin no. pin full name pin select configure register pin44 dcd4#/gpio40 gpio40 index 27h bit0 = 0 index 29h bit7-6 = 00 pin45 ri4#/gpio41 gpio41 pin46 cts4#/gpio42 gpio42 pin47 dtr4#/gpio43 gpio43 pin48 rts4#/gpio44 gpio44 pin49 dsr4#/gpio45 gpio45 pin50 sout4/gpio46 gpio46 pin51 sin4/gpio47 gpio47 7.2.10 multi function register mapping for gpio5x pin no. pin full name pin select configure register pin9 gpio50/densel#/rts6# gpio50 index 27h bit3-2 = 00 index 28h bit6 = 1 and bit1-0 = 00 pin10 gpio51/moa#/sin6 gpio51 pin11 gpio52/drva#/sout6 gpio52 pin12 gpio53/wdata#/dcd6# gpio53 pin13 gpio54/dir#/ri6# gpio54 pin14 gpio55/step#/cts6# gpio55 pin15 gpio56/hdsel#/dtr6 gpio56 pin16 gpio57/wgate#/dsr6# gpio57 7.2.11 multi function register mapping for gpio6x pin no. pin full name pin select configure register pin17 gpio60/rdata#/dcd5# gpio60 index 27h bit3-2 = 00 and bit0 = 0 index 28h bit6 = 1 and bit3-2 = 00 pin18 gpio61/trk0#/ri5# gpio61 pin19 gpio62/index#/cts5# gpio62 pin20 gpio63/wpt#/dtr5# gpio63 pin21 gpio64/dskchg#/dsr5# gpio64 pin74 pme#/gpio65 gpio65 index 27h bit0 = 0 index 2bh bit5 = 1 pin86 dpwrok/gpio66 gpio66 index 27h bit0 = 0 index 2bh bit6 = 1 pin87 s5#/gpio67 gpio67 index 27h bit0 = 0
F81867 dec, 2011 v0.12p 133 index 2bh bit7 = 1 7.2.12 multi function register mapping for gpio7x pin no. pin full name pin select configure register pin103 gpio70/pe/fanctl3/pwm_d ac3 gpio70 index 27h bit3-2 = 00 and bit0 = 0 index 28h bit5 = 1 index 2bh bit0 =0 pin104 gpio71/busy gpio71 index 27h bit3-2 = 00 and bit0 = 0 index 28h bit5 = 1 pin105 gpio72/ack# gpio72 pin106 gpio73/slin# gpio73 pin107 gpio74/init# gpio74 pin108 gpio75/err# gpio75 pin109 gpio76/afd# gpio76 pin110 gpio77/stb# gpio77 7.2.13 multi function register mapping for gpio8x pin no. pin full name pin select configure register pin111 gpio80/pd0 gpio80 index 27h bit3-2 = 00 index 28h bit5 = 1 pin112 gpio81/pd1 gpio81 pin113 gpio82/pd2 gpio82 pin114 gpio83/pd3 gpio83 pin115 gpio84/pd4 gpio84 pin116 gpio85/pd5 gpio85 pin117 gpio86/pd6 gpio86 pin118 gpio87/pd7 gpio87 7.2.14 multi function register mapping for wdt pin no. pin full name pin select configure register pin70 wdtrst#/gpio15 wdtrst# index 27h bit3-2 = 01 and index bit0 = 0 index 2ch bit5 = 0 7.2.15 multi function register mapping for erp, led pin no. pin full name pin select configure register pin52 erp_ctrl0#/gpio00 erp_ctrl0# index 27h bit3-2 and bit0 = 0 index 2ch bit0 = 0 pin53 erp_ctrl1#/gpio01 erp_ctrl1# index 27h bit3-2 and bit0 = 0 index 2ch bit1 = 0
F81867 dec, 2011 v0.12p 134 pin54 sus_warn#/gpio02 sus_warn# index 27h bit3-2 and bit0 = 0 index 2ch bit2 = 0 pin55 sus_ack#/gpio03 sus_ack# index 27h bit3-2 and bit0 = 0 index 2ch bit3 = 0 pin56 slp_sus#/gpio04 slp_sus# index 27h bit3-2 and bit0 = 0 index 2ch bit4 = 0 pin86 dpwrok/gpio66 dpwrok index 27h bit0 = 0 index 2bh bit6 = 0 pin65 gpio10/led_vsb led_vsb index 27h bit3-2 = 01 and bit0 = 0 index 2ch bit1-0 = 00 pin66 gpio11/led_vcc led_vcc pin77 atxpg_in/gpio21 atxpg_in index 27h bit3-2 = 10 and bit0 = 0 index 2ch bit1 = 0 pin78 pwsin#/gpio22 pwsin# index 27h bit3-2 = 10 and bit0 = 0 index 2ch bit2 = 0 pin79 pwsout#/gpio23 pwsout# index 27h bit3-2 = 10 and bit0 = 0 index 2ch bit3 = 0 pin80 s3#/gpio24 s3# index 27h bit3-2 = 10 and bit0 = 0 index 2ch bit4 = 0 pin81 ps_on# /gpio25 ps_on# index 27h bit3-2 = 10 and bit0 = 0 index 2ch bit5 = 0 pin82 pwok/gpio26 pwok index 27h bit3-2 = 10 and bit0 = 0 index 2ch bit6 = 0 pin83 rsmrst#/gpio27 rsmrst# index 27h bit3-2 = 10 and bit0 = 0 index 2ch bit7 = 0 pin87 s5#/gpio67 s5# index 27h bit0 = 0 index 2bh bit7 =0 7.2.16 multi function register mapping for ir pin no. pin full name pin select configure register pin67 pin68 scl/gpio12/irtx sda/gpio13/irrx irtx irrx index 27h bit3-2 = 01 and bit0 = 0 index 29h bit1-0 = 00 index 2ch bit3-2 = 00 7.2.17 multi function register mapping for i2c pin no. pin full name pin select configure register pin61 pin62 mdata/scl mclk/sda scl sda index 27h bit3-2 = 00 index 28h bit4 = 1 pin71 beep/gpio16/sda/cirrx# sda index 27h bit0 = 0
F81867 dec, 2011 v0.12p 135 pin76 alert#/gpio20/scl/cirrx# scl index 29h bit3-2 = 11 7.2.18 multi function register mapping for uart 1 & uart 2 uart 1 & 2 are pure pins. 7.2.19 multi function register mapping for uart 3 pin no. pin full name pin select configure register pin36 dcd3#/gpio30 dcd3# index 27h bit0 = 0 index 29h bit5-4 = 01 only sin3/sout3 available index 29h bit5-4 = 10 only sin3/sout3/rts3# available index 29h bit5-4 = 11 full uart pin37 ri3#/gpio31 ri3# pin38 cts3#/gpio32 cts3# pin39 dtr3#/gpio33 dtr3# pin40 rts3#/gpio34 rts3# pin41 dsr3#/gpio35 dsr3# pin42 sout3/gpio36 sout3 pin43 sin3/gpio37 sin3 7.2.20 multi function register mapping for uart 4 pin no. pin full name pin select configure register pin44 dcd4#/gpio40 dcd4# index 27h bit0 = 0 index 29h bit7-6 = 01 only sin4/sout4 available index 29h bit7-6 = 10 only sin4/sout4/rts4# available index 29h bit7-6 = 11 full uart pin45 ri4#/gpio41 ri4# pin46 cts4#/gpio42 cts4# pin47 dtr4#/gpio43 dtr4# pin48 rts4#/gpio44 rts4# pin49 dsr4#/gpio45 dsr4# pin50 sout4/gpio46 sout4 pin51 sin4/gpio47 sin4 7.2.21 multi function register mapping for uart 5 pin no. pin full name pin select configure register pin17 gpio60/rdata#/dcd5# dcd5# index 27h bit3-2 = 00 index 28h bit3-2 = 01 only sin5/sout5 available index 28h bit3-2 = 10 only sin5/sout5/rts5# available index 28h bit3-2 = 11 full uart pin18 gpio61/trk0#/ri5# ri5# pin19 gpio62/index#/cts5# cts5# pin20 gpio63/wpt#/dtr5# dtr5# pin21 gpio64/dskchg#/dsr5# dsr5# pin57 gpio05/sout5 sout5 pin58 gpio06/sin5 sin5 pin59 gpio07/rts5# rts5#
F81867 dec, 2011 v0.12p 136 7.2.22 multi function register mapping for uart 6 pin no. pin full name pin select configure register pin9 gpio50/densel#/rts6# rts6# index 27h bit3-2 = 00 index 28h bit1-0 = 01 only sin6/sout6 available index 28h bit1-0 = 10 only sin6/sout6/rts6# available index 28h bit1-0 = 11 full uart pin10 gpio51/moa#/sin6 sin6 pin11 gpio52/drva#/sout6 sout6 pin12 gpio53/wdata#/dcd6# dcd6# pin13 gpio54/dir#/ri6# ri6# pin14 gpio55/step#/cts6# cts6# pin15 gpio56/hdsel#/dtr6# dtr6# pin16 gpio57/wgate#/dsr6# dsr6# 7.3 fdc registers (cr00) ?-? reserved or tri-state register 0x[hex] register name default value msb lsb 30 fdc device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 1 61 base address low register 1 1 1 1 0 0 0 0 70 irq channel select register - - - - 0 1 1 0 74 dma channel select register - - - - - 0 1 0 f0 fdd mode register - - - 0 1 1 1 0 f2 fdd drive type register - - - - - - 1 1 f4 fdd selection register - - - 0 0 - 0 0 fdc device enable register ? index 30h bit name r/w reset default description 7-1 reserved - - - reserved 0 fdc_en r/w lreset# 1 0: disable fdc. 1: enable fdc. base address high register ? index 60h bit name r/w reset default description 7-0 base_addr_hi r/w lreset# 03h the msb of fdc base address. base address low register ? index 61h bit name r/w reset default description 7-0 base_addr_lo r/w lreset# f0h the lsb of fdc base address.
F81867 dec, 2011 v0.12p 137 irq channel select register ? index 70h bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 selfdcirq r/w lreset# 06h select the irq channel for fdc. dma channel select register ? index 74h bit name r/w reset default description 7-3 reserved - - - reserved. 2-0 selfdcdma r/w lreset# 010 select the dma channel for fdc. fdd mode register ? index f0h bit name r/w reset default description 7-5 reserved - - - reserved. 4 fdc_sw_wp r/w lreset# 0 fdc software write protect. 0: write protect is determined by wpt# pin. 1: enable write protect. 3-2 if_mode r/w lreset# 11 00: model 30 mode. 01: ps/2 mode. 10: reserved. 11: at mode (default). 1 fdmamode r/w lreset# 1 0: enable burst mode. 1: non-busrt mode (default). 0 reserved r/w - 0 reserved. fdd drive type register ? index f2h bit name r/w reset default description 7-2 reserved - - - reserved. 1-0 fdd_type r/w lreset# 11 fdd drive type. fdd selection register ? index f4h bit name r/w reset default description 7-5 reserved - - - reserved. 4-3 fdd_drt r/w lreset# 00 data rate table select, refer to table a. 00: select regular drives and 2.88 format. 01: reserved. 10: 2 mega tape. 11: reserved. 2 reserved - - - reserved. 1-0 fdd_dt r/w lreset# 00 drive type select, refer to table b. table a data rate table select data rate selected data rate densel fdd_drt[1] fdd_drt[0] datarate1 datarate0 mfm fm
F81867 dec, 2011 v0.12p 138 0 0 0 0 500k 250k 1 0 1 300k 150k 0 1 0 250k 125k 0 1 1 1meg --- 1 0 1 0 0 500k 250k 1 0 1 500k 250k 0 1 0 250k 125k 0 1 1 1meg --- 1 1 0 0 0 500k 250k 1 0 1 2meg --- 0 1 0 250k 125k 0 1 1 1meg --- 1 table b drive type drvden0 remark fdd_dt1 fdd_dt0 0 0 densel 4/2/1 mb 3.5? 2/1 mb 5.25? 1/1.6/1 mb 3.5? (3-mode ) 0 1 datarate1 1 0 densel# 1 1 datarate0 7.4 parallel port registers (cr03) ?-? reserved or tri-state register 0x[hex] register name default value msb lsb 30 parallel port device en able register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 1 61 base address low register 0 1 1 1 1 0 0 0 70 irq channel select register - - - - 0 1 1 1 74 dma channel select register - - - 0 - 0 1 1 f0 prt mode select register 0 1 0 0 0 0 1 0 parallel port device enable register ? index 30h bit name r/w reset default description 7-1 reserved - - - reserved 0 prt_en r/w lreset# 1 0: disable parallel port. 1: enable parallel port.
F81867 dec, 2011 v0.12p 139 base address high register ? index 60h bit name r/w reset default description 7-0 base_addr_hi r/w lreset# 03h the msb of parallel port base address. base address low register ? index 61h bit name r/w reset default description 7-0 base_addr_lo r/w lreset# 78h the lsb of parallel port base address. irq channel select register ? index 70h bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 selprtirq r/w lreset# 7h select the irq channel for parallel port. dma channel select register ? index 74h bit name r/w reset default description 7-5 reserved - - - reserved. 4 ecp_dma_mode r/w lreset# 0 0: non-burst mode dma. 1: enable burst mode dma. 3 reserved - - - reserved. 2-0 selprtdma r/w lreset# 011 select the dma channel for parallel port. prt mode select register ? index f0h bit name r/w reset default description 7 spp_irq_mode r/w lreset# 0 interrupt mode in non-ecp mode. 0: level mode. 1: pulse mode. 6-3 ecp_fifo_thr r/w lreset# 1000 ecp fifo threshold. 2-0 prt_mode r/w lreset# 010 000: standard and bi-direction (spp) mode. 001: epp 1.9 and spp mode. 010: ecp mode (default). 011: ecp and epp 1.9 mode. 100: printer mode. 101: epp 1.7 and spp mode. 110: reserved. 111: ecp and epp1.7 mode.
F81867 dec, 2011 v0.12p 140 7.5 hardware monitor registers (cr04) ?-? reserved or tri-state register 0x[hex] register name default value msb lsb 30 h/w monitor device enabl e register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 0 61 base address low register 1 0 0 1 0 1 0 1 70 irq channel select register - - - - 0 0 0 0 hardware monitor device enable register ? index 30h bit name r/w reset default description 7-1 reserved - - - reserved 0 hm_en r/w lreset# 1 0: disable hardware monitor. 1: enable hardware monitor. base address high register ? index 60h bit name r/w reset default description 7-0 base_addr_hi r/w lreset# 02h the msb of hardware monitor base address. base address low register ? index 61h bit name r/w reset default description 7-0 base_addr_lo r/w lreset# 95h the lsb of hardware monitor base address. irq channel select register ? index 70h bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 selhmirq r/w lreset# 0000 select the irq channel for hardware monitor. 7.6 kbc registers (cr05) ?-? reserved or tri-state register 0x[hex] register name default value msb lsb 30 h/w monitor device enabl e register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 0 61 base address low register 1 0 0 1 0 1 0 1 70 irq channel select register - - - - 0 0 0 0 fe ps/2 swap register 0 - - 0 0 0 0 1
F81867 dec, 2011 v0.12p 141 kbc device enable register ? index 30h bit name r/w reset default description 7-1 reserved - - - reserved 0 kbc_en r/w 3vcc 1 0: disable kbc. 1: enable kbc. base address high register ? index 60h bit name r/w reset default description 7-0 base_addr_hi r/w lreset# 00h the msb of kbc command port address. the address of data port is command port address + 4 base address low register ? index 61h bit name r/w reset default description 7-0 base_addr_lo r/w lreset# 60h the lsb of kbc command port address. the address of data port is command port address + 4. kb irq channel select register ? index 70h bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 selkirq r/w lreset# 0h select the irq channel for keyboard interrupt. mouse irq channel select register ? index 72h bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 selmirq r/w lreset# 0h select the irq channel for ps/2 mouse interrupt. ps/2 swap register ? index feh bit name r/w reset default description 7-5 reserved - - - reserved 4 kb_mo_swap r/w vbat 0 keyboard mouse swap. 0: keyboard/mouse is not swapped. 1: keyboard/mouse is swapped. this bit could be programmed by user. if auto_det_en is set, this bit is also updated by hardware. 3-0 kbc_test_bit r/w vbat 3h fintek test mode bits.
F81867 dec, 2011 v0.12p 142 7.7 gpio registers (cr06) 7.7.1 gpio configuration registers ?-? reserved or tri-state register 0x[hex] register name default value msb lsb 30 gpio device enable register - - - - - - - 0 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 1 1 0 0 0 0 0 gpio device enable register ? index 30h bit name r/w reset default description 7-1 reserved - - - reserved 0 gpio_en r/w lreset# 0 0: disable gpio i/o port. 1: enable gpio i/o port. base address high register ? index 60h bit name r/w reset default description 7-0 gp_base_addr_hi r/w lreset# 00h the msb of gpio i/o port address. base address low register ? index 61h bit name r/w reset default description 7-0 base_addr_lo r/w lreset# 60h the lsb of kbc data port address. when gpio_dec_range is ?0?, only 8 bytes are decoded: base + 0: index port. base + 1: data port. base + 2: gpio8 data register. base + 3: gpio7 data register. base + 4: gpio6 data register. base + 5: gpio5 data register. base + 6: gpio0 data register. base + 7: gpio1 data register. if gpio_dec_range is set to ?1 ?, more 8 bytes are decoded: base + 8: gpio2 data register. base + 9: gpio3 data register. base + 10: gpio4 data register. otherwise: reserved. there are three ways to access the gpio registers. 1. use configuration regi ster port 0x4e/0x4f (or 0x2e/0x2f), the ldn for gpio is 0x06. 2. use gpio index/data port. write index to index port first and then read/write the register. 3. use digital i/o port. the way only ac cess gpio data register. write data to this port will control the data output regi ster. and read this port will read the pin status register.
F81867 dec, 2011 v0.12p 143 7.7.2 gpio irq channel sele ct configuration registers register 0x[hex] register name default value msb lsb 70 gpio0 irq channel select register - - - - 0 0 0 1 71 gpio1 irq channel select register - - - - 0 0 0 1 72 gpio5 irq channel select register - - - - 0 0 0 1 73 gpio8 irq channel select register - - - - 0 0 0 1 gpio0 irq channel select register ? index 70h bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 selgp0irq r/w lreset# 1h select the irq chan nel for gpio0 interrupt. gpio1 irq channel select register ? index 71h bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 selgp1irq r/w lreset# 1h select the irq chan nel for gpio1 interrupt. gpio5 irq channel select register ? index 72h bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 selgp5irq r/w lreset# 1h select the irq chan nel for gpio5 interrupt. gpio8 irq channel select register ? index 73h bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 selgp8irq r/w lreset# 1h select the irq chan nel for gpio8 interrupt. 7.7.3 gpio irq sharing configuration registers register 0x[hex] register name default value msb lsb 7e gpio irq share enable register - - - - 0 0 0 0 7f gpio irq share mode register 0 0 0 0 0 0 0 0 gpio irq sharing enable register index 7eh bit name r/w reset default description 7-4 reserved - - - reserved. 3 gp8_irq_share r/w lreset# 0 0: gpio8 irq is not sharing with other devices. 1: gpio8 irq is sharing with other devices.
F81867 dec, 2011 v0.12p 144 2 gp5_irq_share r/w lreset# 0 0: gpio5 irq is not sharing with other devices.. 1: gpio5 irq is sharing with other devices. 1 gp1_irq_share r/w lreset# 0 0: gpio1 irq is not sharing with other devices. 1: gpio1 irq is sharing with other devices. 0 gp0_irq_share r/w lreset# 0 0: gpio0 irq is not sharing with other devices. 1: gpio0 irq is sharing with other devices. gpio irq sharing mode register index 7fh bit name r/w reset default description 7-6 gp8_irq_mode r/w lreset# 0 gpio8 irq sharing mode: 00 : sharing irq active low level. 01 : sharing irq active high edge. 10 : sharing irq active high level. 11 : reserved. this bit is effective when irq is sharing with other device (gp8_irq_share is ?1?). 5-4 gp5_irq_mode r/w lreset# 0 gpio5 irq sharing mode: 00 : sharing irq active low level. 01 : sharing irq active high edge. 10 : sharing irq active high level. 11 : reserved. this bit is effective when irq is sharing with other device (gp5_irq_share is ?1?). 3-2 gp1_irq_mode r/w lreset# 0 gpio1 irq sharing mode: 00 : sharing irq active low level. 01 : sharing irq active high edge. 10 : sharing irq active high level. 11 : reserved. this bit is effective when irq is sharing with other device (gp1_irq_share is ?1?).
F81867 dec, 2011 v0.12p 145 1-0 gp0_irq_mode r/w lreset# 0 gpio0 irq sharing mode: 00 : sharing irq active low level. 01 : sharing irq active high edge. 10 : sharing irq active high level. 11 : reserved. this bit is effective when irq is sharing with other device (gp0_irq_share is ?1?). 7.7.4 gpio0x configuration registers register 0x[hex] register name default value msb lsb f0 gpio0 output enable register 0 0 0 0 0 0 0 0 f1 gpio0 output data register 0 0 0 0 1 1 1 1 f2 gpio0 pin status register - - - - - - - - f3 gpio0 drive enable register 0 0 0 0 0 0 0 0 f4 gpio0 output mode 1 register 0 0 0 0 0 0 0 0 f5 gpio0 output mode 2 register 0 0 0 0 0 0 0 0 f6 gpio0 pulse width select 1 register 0 0 0 0 0 0 0 0 f7 gpio0 pulse width select 2 register 0 0 0 0 0 0 0 0 f8 gpio0 smi enable register 0 0 0 0 0 0 0 0 f9 gpio0 smi status register 0 0 0 0 0 0 0 0 gpio0 output enable register ? index f0h bit name r/w reset default description 7 gpio07_oe r/w 5vsb 0 0: gpio07 is input. 1: gpio07 is output. 6 gpio06_oe r/w 5vsb 0 0: gpio06 is input. 1: gpio06 is output. 5 gpio05_oe r/w 5vsb 0 0: gpio05 is input. 1: gpio05 is output. 4 gpio04_oe r/w 5vsb 0 0: gpio04 is input. 1: gpio04 is output. 3 gpio03_oe r/w 5vsb 0 0: gpio03 is input. 1: gpio03 is output. 2 gpio02_oe r/w 5vsb 0 0: gpio02 is input. 1: gpio02 is output. 1 gpio01_oe r/w 5vsb 0 0: gpio01 is input. 1: gpio01 is output.
F81867 dec, 2011 v0.12p 146 0 gpio00_oe r/w 5vsb 0 0: gpio00 is input. 1: gpio00 is output. gpio0 output data register ? index f1h (this byte could be also written by base address + 6) bit name r/w reset default description 7 gpio07_val r/w 5vsb 0 gpio07 supports pulse mode. when pulse mode is selected, write ?1? to this bit will assert a pulse from gpio07. auto clear when pulse is finished. when level mode is selected, write 0/1 to this bit will set the level of gpio07. 0: outputs 0 when in output mode. 1: outputs 1 when in output mode. gpio 07 will be tri-state if gpio07_drv is clear to ?0?. 6 gpio06_val r/w 5vsb 0 gpio06 supports pulse mode. when pulse mode is selected, write ?1? to this bit will assert a pulse from gpio06. auto clear when pulse is finished. when level mode is selected, write 0/1 to this bit will set the level of gpio06. 0: outputs 0 when in output mode. 1: outputs 1 when in output mode. gpio 06 will be tri-state if gpio06_drv is clear to ?0?. 5 gpio05_val r/w 5vsb 0 gpio05 supports pulse mode. when pulse mode is selected, write ?1? to this bit will assert a pulse from gpio05. auto clear when pulse is finished. when level mode is selected, write 0/1 to this bit will set the level of gpio05. 0: outputs 0 when in output mode. 1: outputs 1 when in output mode. gpio 05 will be tri-state if gpio05_drv is clear to ?0?. 4 gpio04_val r/w 5vsb 0 gpio04 supports pulse mode. when pulse mode is selected, write ?1? to this bit will assert a pulse from gpio04. auto clear when pulse is finished. when level mode is selected, write 0/1 to this bit will set the level of gpio04. 0: outputs 0 when in output mode. 1: outputs 1 when in output mode. gpio 04 will be tri-state if gpio04_drv is clear to ?0?.1: gpio04 outputs 1 when in output mode. 3 gpio03_val r/w 5vsb 1 0: gpio03 outputs 0 when in output mode. 1: gpio03 outputs 1 when in output mode. 2 gpio02_val r/w 5vsb 1 0: gpio02 outputs 0 when in output mode. 1: gpio02 outputs 1 when in output mode. 1 gpio01_val r/w 5vsb 1 0: gpio01 outputs 0 when in output mode. 1: gpio01 outputs 1 when in output mode. 0 gpio00_val r/w 5vsb 1 0: gpio00 outputs 0 when in output mode. 1: gpio00 outputs 1 when in output mode. gpio0 pin status register ? index f2h (this byte could be also read by base address + 6) bit name r/w reset default description 7 gpio07_in r - - the pin status of gpio07/rts5#. 6 gpio06_in r - - the pin status of gpio06/sin5. 5 gpio05_in r - - the pin status of gpio05/sout5. 4 gpio04_in r - - the pin status of slp_sus#/gpio04.
F81867 dec, 2011 v0.12p 147 3 gpio03_in r - - the pin status of sus_ack#/gpio03. 2 gpio02_in r - - the pin status of sus_warn#/gpio02. 1 gpio01_in r - - the pin status of erp_ctrl1#/gpio01. 0 gpio00_in r - - the pin status of erp_ctrl0#/gpio00. gpio0 drive enable register ? index f3h bit name r/w reset default description 7 gpio07_drv_en r/w 5vsb 0 gpio07 drive enable. 0: gpio07 is open drain. 1: gpio07 is push pull. 6 gpio06_drv_en r/w 5vsb 0 gpio06 drive enable. 0: gpio06 is open drain. 1: gpio06 is push pull. 5 gpio05_drv_en r/w 5vsb 0 gpio05 drive enable. 0: gpio05 is open drain. 1: gpio05 is push pull. 4 gpio04_drv_en r/w 5vsb 0 gpio04 drive enable. 0: gpio04 is open drain. 1: gpio04 is push pull. 3 gpio03_drv_en r/w 5vsb 0 gpio03 drive enable. 0: gpio03 is open drain. 1: gpio03 is push pull. 2 gpio02_drv_en r/w 5vsb 0 gpio02 drive enable. 0: gpio02 is open drain. 1: gpio02 is push pull. 1 gpio01_drv_en r/w 5vsb 0 gpio01 drive enable. 0: gpio01 is open drain. 1: gpio01 is push pull. 0 gpio00_drv_en r/w 5vsb 0 gpio00 drive enable. 0: gpio00 is open drain. 1: gpio00 is push pull. gpio0 output mode 1 register ? index f4h bit name r/w reset default description 7-6 gpio03_mode r/w 5vsb 00b gpio03 output mode select: 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. the pulse width is determined by gpio03_pw_sel. 5-4 gpio02_mode r/w 5vsb 00b gpio02 output mode select: 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. the pulse width is determined by gpio02_pw_sel.
F81867 dec, 2011 v0.12p 148 3-2 gpio01_mode r/w 5vsb 00b gpio01 output mode select: 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. the pulse width is determined by gpio01_pw_sel. 1-0 gpio00_mode r/w 5vsb 00b gpio00 output mode select: 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. the pulse width is determined by gpio00_pw_sel. gpio0 output mode 2 register ? index f5h bit name r/w reset default description 7-6 gpio07_mode r/w 5vsb 00b gpio07 output mode select: 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. the pulse width is determined by gpio07_pw_sel. 5-4 gpio06_mode r/w 5vsb 00b gpio06 output mode select: 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. the pulse width is determined by gpio06_pw_sel. 3-2 gpio05_mode r/w 5vsb 00b gpio05 output mode select: 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. the pulse width is determined by gpio05_pw_sel. 1-0 gpio04_mode r/w 5vsb 00b gpio04 output mode select: 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. the pulse width is determined by gpio04_pw_sel.
F81867 dec, 2011 v0.12p 149 gpio0 pulse width select 1 register ? index f6h bit name r/w reset default description 7-6 gpio03_pw_sel r/w 5vsb 00b gpio03 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. 5-4 gpio02_pw_sel r/w 5vsb 00b gpio02 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. 3-2 gpio01_pw_sel r/w 5vsb 00b gpio01 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. 1-0 gpio00_pw_sel r/w 5vsb 00b gpio00 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. gpio0 pulse width select 2 register ? index f7h bit name r/w reset default description 7-6 gpio07_pw_sel r/w 5vsb 00b gpio07 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. 5-4 gpio06_pw_sel r/w 5vsb 00b gpio06 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. 3-2 gpio05_pw_sel r/w 5vsb 00b gpio05 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. 1-0 gpio04_pw_sel r/w 5vsb 00b gpio04 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms.
F81867 dec, 2011 v0.12p 150 gpio0 smi enable register ? index f8h bit name r/w reset default description 7 gpio07_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio07_smi_st is set. 6 gpio06_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio06_smi_st is set. 5 gpio05_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio05_smi_st is set. 4 gpio04_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio04_smi_st is set. 3 gpio03_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio03_smi_st is set. 2 gpio02_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio02_smi_st is set. 1 gpio01_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio01_smi_st is set. 0 gpio00_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio00_smi_st is set. gpio0 smi status register ? index f9h bit name r/w reset default description 7 gpio07_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio07 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 6 gpio06_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio06 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 5 gpio05_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio05 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 4 gpio04_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio04 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 3 gpio03_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio03 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 2 gpio02_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio02 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 1 gpio01_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio01 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 0 gpio00_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio00 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status.
F81867 dec, 2011 v0.12p 151 7.7.5 gpio1x configuration registers register 0x[hex] register name default value msb lsb e0 gpio1 output enable register 0 0 0 0 0 0 0 0 e1 gpio1 output data register 1 1 1 1 1 1 1 1 e2 gpio1 pin status register - - - - - - - - e3 gpio1 drive enable register 0 0 0 0 0 0 0 0 e8 gpio1 smi enable register 0 0 0 0 0 0 0 0 e9 gpio1 smi status register 0 0 0 0 0 0 0 0 gpio1 output enable register ? index e0h bit name r/w reset default description 7 gpio17_oe r/w 5vsb 0 0: gpio17 is in input mode. 1: gpio17 is in output mode. 6 gpio16_oe r/w 5vsb 0 0: gpio16 is in input mode. 1: gpio16 is in output mode. 5 gpio15_oe r/w 5vsb 0 0: gpio15 is in input mode. 1: gpio15 is in output mode. 4 gpio14_oe r/w 5vsb 0 0: gpio14 is in input mode. 1: gpio14 is in output mode. 3 gpio13_oe r/w 5vsb 0 0: gpio13 is in input mode. 1: gpio13 is in output mode. 2 gpio12_oe r/w 5vsb 0 0: gpio12 is in input mode. 1: gpio12 is in output mode. 1 gpio11_oe r/w 5vsb 0 0: gpio11 is in input mode. 1: gpio11 is in output mode. 0 gpio10_oe r/w 5vsb 0 0: gpio10 is in input mode. 1: gpio10 is in output mode. gpio1 output data register ? index e1h (this byte could be also written by base address + 7) bit name r/w reset default description 7 gpio17_val r/w 5vsb 1 0: gpio17 outputs 0 when in output mode. 1: gpio17 outputs1 when in output mode. 6 gpio16_val r/w 5vsb 1 0: gpio16 outputs 0 when in output mode. 1: gpio16 outputs1 when in output mode. 5 gpio15_val r/w 5vsb 1 0: gpio15 outputs 0 when in output mode. 1: gpio15 outputs 1 when in output mode. 4 gpio14_val r/w 5vsb 1 0: gpio14 outputs 0 when in output mode. 1: gpio14 outputs 1 when in output mode. 3 gpio13_val r/w 5vsb 1 0: gpio13 outputs 0 when in output mode. 1: gpio13 outputs 1 when in output mode.
F81867 dec, 2011 v0.12p 152 2 gpio12_val r/w 5vsb 1 0: gpio12 outputs 0 when in output mode. 1: gpio12 outputs 1 when in output mode. 1 gpio11_val r/w 5vsb 1 0: gpio11 outputs 0 when in output mode. 1: gpio11 outputs 1 when in output mode. 0 gpio10_val r/w 5vsb 1 0: gpio10 outputs 0 when in output mode. 1: gpio10 outputs 1 when in output mode. gpio1 pin status register ? index e2h (this byte could be also read by base address + 7) bit name r/w reset default description 7 gpio17_in r - - the pin status of peci/gpio17. 6 gpio16_in r - - the pin status of beep/gpio16/sda/cirrx#. 5 gpio15_in r - - the pin status of wdtrst#/gpio15. 4 gpio14_in r - - the pin status of gpio14/at_atx_trap. 3 gpio13_in r - - the pin status of sda/gpio13/irrx. 2 gpio12_in r - - the pin status of scl/gpio12/irtx 1 gpio11_in r - - the pin status of gpio11/led_vcc. 0 gpio10_in r - - the pin status of gpio10/led_vsb. gpio1 drive enable register ? index e3h bit name r/w reset default description 7 gpio17_drv_en r/w 5vsb 0 0: gpio17 is open drain in output mode. 1: gpio17 is push pull in output mode. 6 gpio16_drv_en r/w 5vsb 0 0: gpio16 is open drain in output mode. 1: gpio16 is push pull in output mode. 5 gpio15_drv_en r/w 5vsb 0 0: gpio15 is open drain in output mode. 1: gpio15 is push pull in output mode. 4 gpio14_drv_en r/w 5vsb 0 0: gpio14 is open drain in output mode. 1: gpio14 is push pull in output mode. 3 gpio13_drv_en r/w 5vsb 0 0: gpio13 is open drain in output mode. 1: gpio13 is push pull in output mode. 2 gpio12_drv_en r/w 5vsb 0 0: gpio12 is open drain in output mode. 1: gpio12 is push pull in output mode. 1 gpio11_drv_en r/w vbat 0 0: gpio11 is open drain in output mode. 1: gpio11 is push pull in output mode. this bit is powered by vbat. 0 gpio10_drv_en r/w vbat 0 0: gpio10 is open drain in output mode. 1: gpio10 is push pull in output mode. this bit is powered by vbat. gpio1 smi enable register ? index e8h bit name r/w reset default description 7 gpio17_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio17_smi_st is set. 6 gpio16_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio16_smi_st is set.
F81867 dec, 2011 v0.12p 153 5 gpio15_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio15_smi_st is set. 4 gpio14_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio14_smi_st is set. 3 gpio13_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio13_smi_st is set. 2 gpio12_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio12_smi_st is set. 1 gpio11_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio11_smi_st is set. 0 gpio10_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio10_smi_st is set. gpio1 smi status register ? index e9h bit name r/w reset default description 7 gpio17_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio17 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 6 gpio16_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio16 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 5 gpio15_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio15 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 4 gpio14_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio14 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 3 gpio13_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio13 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 2 gpio12_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio12 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 1 gpio11_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio11 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 0 gpio10_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio10 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status.
F81867 dec, 2011 v0.12p 154 7.7.6 gpio2x configuration registers register 0x[hex] register name default value msb lsb d0 gpio2 output enable register 0 0 0 0 0 0 0 0 d1 gpio2 output data register 1 1 1 1 1 1 1 1 d2 gpio2 pin status register - - - - - - - - d3 gpio2 drive enable register 0 0 0 0 0 0 0 0 gpio2 output enable register ? index d0h bit name r/w reset default description 7 gpio27_oe r/w 5vsb 0 0: gpio27 is in input mode. 1: gpio27 is in output mode. 6 gpio26_oe r/w 5vsb 0 0: gpio26 is in input mode. 1: gpio26 is in output mode. 5 gpio25_oe r/w 5vsb 0 0: gpio25 is in input mode. 1: gpio25 is in output mode. 4 gpio24_oe r/w 5vsb 0 0: gpio24 is in input mode. 1: gpio24 is in output mode. 3 gpio23_oe r/w 5vsb 0 0: gpio23 is in input mode. 1: gpio23 is in output mode. 2 gpio22_oe r/w 5vsb 0 0: gpio22 is in input mode. 1: gpio22 is in output mode. 1 gpio21_oe r/w 5vsb 0 0: gpio21 is in input mode. 1: gpio21 is in output mode. 0 gpio20_oe r/w 5vsb 0 0: gpio20 is in input mode. 1: gpio20 is in output mode. gpio2 output data register ? index d1h (this byte could be also written by base address + 8 if gpio_dec_range is set to ?1?) bit name r/w reset default description 7 gpio27_val r/w 5vsb 1 0: gpio27 outputs 0 when in output mode. 1: gpio27 outputs1 when in output mode. 6 gpio26_val r/w 5vsb 1 0: gpio26 outputs 0 when in output mode. 1: gpio26 outputs1 when in output mode. 5 gpio25_val r/w 5vsb 1 0: gpio25 outputs 0 when in output mode. 1: gpio25 outputs 1 when in output mode. 4 gpio24_val r/w 5vsb 1 0: gpio24 outputs 0 when in output mode. 1: gpio24 outputs 1 when in output mode. 3 gpio23_val r/w 5vsb 1 0: gpio23 outputs 0 when in output mode. 1: gpio23 outputs 1 when in output mode. 2 gpio22_val r/w 5vsb 1 0: gpio22 outputs 0 when in output mode. 1: gpio22 outputs 1 when in output mode. 1 gpio21_val r/w 5vsb 1 0: gpio21 outputs 0 when in output mode. 1: gpio21 outputs 1 when in output mode.
F81867 dec, 2011 v0.12p 155 0 gpio20_val r/w 5vsb 1 0: gpio20 outputs 0 when in output mode. 1: gpio20 outputs 1 when in output mode. gpio2 pin status register ? index d2h (this byte could be also read by base address + 8 if gpio_dec_range is set to ?1?) bit name r/w reset default description 7 gpio27_in r - - the pin status of rsmrst#/gpio27. 6 gpio26_in r - - the pin status of pwok/gpio26. 5 gpio25_in r - - the pin status of ps_on#/gpio25. 4 gpio24_in r - - the pin status of s3#/gpio24. 3 gpio23_in r - - the pin status of pwsout#/gpio23. 2 gpio22_in r - - the pin status of pwsin#/gpio22. 1 gpio21_in r - - the pin status of atxpg_in#/gpio21. 0 gpio20_in r - - the pin status of alert#/gpio20/scl/cirrx#. gpio2 drive enable register ? index d3h bit name r/w reset default description 7 gpio27_drv_en r/w 5vsb 0 0: gpio27 is open drain in output mode. 1: gpio27 is push pull in output mode. 6 gpio26_drv_en r/w 5vsb 0 0: gpio26 is open drain in output mode. 1: gpio26 is push pull in output mode. 5 gpio25_drv_en r/w 5vsb 0 0: gpio25 is open drain in output mode. 1: gpio25 is push pull in output mode. 4 gpio24_drv_en r/w 5vsb 0 0: gpio24 is open drain in output mode. 1: gpio24 is push pull in output mode. 3 gpio23_drv_en r/w 5vsb 0 0: gpio23 is open drain in output mode. 1: gpio23 is push pull in output mode. 2 gpio22_drv_en r/w 5vsb 0 0: gpio22 is open drain in output mode. 1: gpio22 is push pull in output mode. 1 gpio21_drv_en r/w 5vsb 0 0: gpio21 is open drain in output mode. 1: gpio21 is push pull in output mode. 0 gpio20_drv_en r/w 5vsb 0 0: gpio20 is open drain in output mode. 1: gpio20 is push pull in output mode. 7.7.7 gpio3x configuration registers register 0x[hex] register name default value msb lsb c0 gpio3 output enable register 0 0 0 0 0 0 0 0 c1 gpio3 output data register 1 1 1 1 1 1 1 1 c2 gpio3 pin status register - - - - - - - - c3 gpio3 drive enable register 0 0 0 0 0 0 0 0
F81867 dec, 2011 v0.12p 156 gpio3 output enable register ? index c0h bit name r/w reset default description 7 gpio37_oe r/w lreset# 0 0: gpio37 is input. 1: gpio37 is output. 6 gpio36_oe r/w lreset# 0 0: gpio36 is input. 1: gpio36 is output. 5 gpio35_oe r/w lreset# 0 0: gpio35 is input. 1: gpio35 is output. 4 gpio34_oe r/w lreset# 0 0: gpio34 is input. 1: gpio34 is output. 3 gpio33_oe r/w lreset# 0 0: gpio33 is input. 1: gpio33 is output. 2 gpio32_oe r/w lreset# 0 0: gpio32 is input. 1: gpio32 is output. 1 gpio31_oe r/w lreset# 0 0: gpio31 is input. 1: gpio31 is output. 0 gpio30_oe r/w lreset# 0 0: gpio30 is input. 1: gpio30 is output. gpio3 output data register ? index c1h (this byte could be also written by base address + 9 if gpio_dec_range is set to ?1?) bit name r/w reset default description 7 gpio37_val r/w lreset# 1 0: gpio37 outputs 0 when in output mode. 1: gpio37 outputs 1 when in output mode. 6 gpio36_val r/w lreset# 1 0: gpio36 outputs 0 when in output mode. 1: gpio36 outputs 1 when in output mode. 5 gpio35_val r/w lreset# 1 0: gpio35 outputs 0 when in output mode. 1: gpio35 outputs 1 when in output mode. 4 gpio34_val r/w lreset# 1 0: gpio34 outputs 0 when in output mode. 1: gpio34 outputs 1 when in output mode. 3 gpio33_val r/w lreset# 1 0: gpio33 outputs 0 when in output mode. 1: gpio33 outputs 1 when in output mode. 2 gpio32_val r/w lreset# 1 0: gpio32 outputs 0 when in output mode. 1: gpio32 outputs 1 when in output mode. 1 gpio31_val r/w lreset# 1 0: gpio31 outputs 0 when in output mode. 1: gpio31 outputs 1 when in output mode. 0 gpio30_val r/w lreset# 1 0: gpio30 outputs 0 when in output mode. 1: gpio30 outputs 1 when in output mode. gpio3 pin status register ? index c2h (this byte could be also read by base address + 9 if gpio_dec_range is set to ?1?) bit name r/w reset default description 7 gpio37_in r - - the pin status of sin3/gpio37. 6 gpio36_in r - - the pin status of sout3/gpio36.
F81867 dec, 2011 v0.12p 157 5 gpio35_in r - - the pin status of dsr3#/gpio35. 4 gpio34_in r - - the pin status of rts3#/gpio34. 3 gpio33_in r - - the pin status of dtr3#/gpio33. 2 gpio32_in r - - the pin status of cts3#/gpio32. 1 gpio31_in r - - the pin status of ri3#/gpio31. 0 gpio30_in r - - the pin status of dcd3#/gpio30. gpio3 drive enable register ? index c3h bit name r/w reset default description 7 gpio37_drv_en r/w lreset# 0 gpio37 drive enable. 0: gpio37 is open drain. 1: gpio37 is push pull. 6 gpio36_drv_en r/w lreset# 0 gpio36 drive enable. 0: gpio36 is open drain. 1: gpio36 is push pull. 5 gpio35_drv_en r/w lreset# 0 gpio35 drive enable. 0: gpio35 is open drain. 1: gpio35 is push pull. 4 gpio34_drv_en r/w lreset# 0 gpio34 drive enable. 0: gpio34 is open drain. 1: gpio34 is push pull. 3 gpio33_drv_en r/w lreset# 0 gpio33 drive enable. 0: gpio33 is open drain. 1: gpio33 is push pull. 2 gpio32_drv_en r/w lreset# 0 gpio32 drive enable. 0: gpio32 is open drain. 1: gpio32 is push pull. 1 gpio31_drv_en r/w lreset# 0 gpio31 drive enable. 0: gpio31 is open drain. 1: gpio31 is push pull. 0 gpio30_drv_en r/w lreset# 0 gpio30 drive enable. 0: gpio30 is open drain. 1: gpio30 is push pull. 7.7.8 gpio4x configuration registers register 0x[hex] register name default value msb lsb b0 gpio4 output enable register 0 0 0 0 0 0 0 0 b1 gpio4 output data register 1 1 1 1 1 1 1 1 b2 gpio4 pin status register - - - - - - - - b3 gpio4 driver enable register 0 0 0 0 0 0 0 0
F81867 dec, 2011 v0.12p 158 gpio4 output enable register ? index b0h bit name r/w reset default description 7 gpio47_oe r/w lreset# 0 0: gpio47 is input. 1: gpio47 is output. 6 gpio46_oe r/w lreset# 0 0: gpio46 is input. 1: gpio46 is output. 5 gpio45_oe r/w lreset# 0 0: gpio45 is input. 1: gpio45 is output. 4 gpio44_oe r/w lreset# 0 0: gpio44 is input. 1: gpio44 is output. 3 gpio43_oe r/w lreset# 0 0: gpio43 is input. 1: gpio43 is output. 2 gpio42_oe r/w lreset# 0 0: gpio42 is input. 1: gpio42 is output. 1 gpio41_oe r/w lreset# 0 0: gpio41 is input. 1: gpio41 is output. 0 gpio40_oe r/w lreset# 0 0: gpio40 is input. 1: gpio40 is output. gpio4 output data register ? index b1h (this byte could be also written by base address + 10 if gpio_dec_range is set to ?1?) bit name r/w reset default description 7 gpio47_data r/w lreset# 1 0: gpio47 outputs 0 when in output mode. 1: gpio47 outputs 1 when in output mode. 6 gpio46_data r/w lreset# 1 0: gpio46 outputs 0 when in output mode. 1: gpio46 outputs 1 when in output mode. 5 gpio45_data r/w lreset# 1 0: gpio45 outputs 0 when in output mode. 1: gpio45 outputs 1 when in output mode. 4 gpio44_data r/w lreset# 1 0: gpio44 outputs 0 when in output mode. 1: gpio44 outputs 1 when in output mode. 3 gpio43_data r/w lreset# 1 0: gpio43 outputs 0 when in output mode. 1: gpio43 outputs 1 when in output mode. 2 gpio42_data r/w lreset# 1 0: gpio42 outputs 0 when in output mode. 1: gpio42 outputs 1 when in output mode. 1 gpio41_data r/w lreset# 1 0: gpio41 outputs 0 when in output mode. 1: gpio41 outputs 1 when in output mode. 0 gpio40_data r/w lreset# 1 0: gpio40 outputs 0 when in output mode. 1: gpio40 outputs 1 when in output mode. gpio4 pin status register ? index b2h (this byte could be also read by base address + 10 if gpio_dec_range is set to ?1?) bit name r/w reset default description 7 gpio47_st r - - the pin status of sin4/gpio47. 6 gpio46_st r - - the pin status of sout4/gpio46. 5 gpio45_st r - - the pin status of dsr4#/gpio45.
F81867 dec, 2011 v0.12p 159 4 gpio44_st r - - the pin status of rts4#/gpio44. 3 gpio43_st r - - the pin status of dtr4#/gpio43. 2 gpio42_st r - - the pin status of cts4#/gpio42. 1 gpio41_st r - - the pin status of ri4#/gpio41. 0 gpio40_st r - - the pin status of dcd4#/gpio40. gpio4 drive enable register ? index b3h bit name r/w reset default description 7 gpio47_drv_en r/w lreset# 0 gpio47 drive enable. 0: gpio47 is open drain. 1: gpio47 is push pull. 6 gpio46_drv_en r/w lreset# 0 gpio46 drive enable. 0: gpio46 is open drain. 1: gpio46 is push pull. 5 gpio45_drv_en r/w lreset# 0 gpio45 drive enable. 0: gpio45 is open drain. 1: gpio45 is push pull. 4 gpio44_drv_en r/w lreset# 0 gpio44 drive enable. 0: gpio44 is open drain. 1: gpio44 is push pull. 3 gpio43_drv_en r/w lreset# 0 gpio43 drive enable. 0: gpio43 is open drain. 1: gpio43 is push pull. 2 gpio42_drv_en r/w lreset# 0 gpio42 drive enable. 0: gpio42 is open drain. 1: gpio42 is push pull. 1 gpio41_drv_en r/w lreset# 0 gpio41 drive enable. 0: gpio41 is open drain. 1: gpio41 is push pull. 0 gpio40_drv_en r/w lreset# 0 gpio40 drive enable. 0: gpio40 is open drain. 1: gpio40 is push pull. 7.7.9 gpio5x configuration registers register 0x[hex] register name default value msb lsb a0 gpio5 output enable register 0 0 0 0 0 0 0 0 a1 gpio5 output data register 1 1 1 1 1 1 1 1 a2 gpio5 pin status register - - - - - - - - a3 gpio5 drive enable register 0 0 0 0 0 0 0 0 a8 gpio5 smi enable register 0 0 0 0 0 0 0 0 a9 gpio5 smi status register 0 0 0 0 0 0 0 0
F81867 dec, 2011 v0.12p 160 gpio5 output enable register ? index a0h bit name r/w reset default description 7 gpio57_oe r/w lreset# 0 0: gpio57 is in input mode. 1: gpio57 is in output mode. 6 gpio56_oe r/w lreset# 0 0: gpio56 is in input mode. 1: gpio56 is in output mode. 5 gpio55_oe r/w lreset# 0 0: gpio55 is in input mode. 1: gpio55 is in output mode. 4 gpio54_oe r/w lreset# 0 0: gpio54 is in input mode. 1: gpio54 is in output mode. 3 gpio53_oe r/w lreset# 0 0: gpio53 is in input mode. 1: gpio53 is in output mode. 2 gpio52_oe r/w lreset# 0 0: gpio52 is in input mode. 1: gpio52 is in output mode. 1 gpio51_oe r/w lreset# 0 0: gpio51 is in input mode. 1: gpio51 is in output mode. 0 gpio50_oe r/w lreset# 0 0: gpio50 is in input mode. 1: gpio50 is in output mode. gpio5 output data register ? index a1h (this byte could be also written by base address + 5 ) bit name r/w reset default description 7 gpio57_data r/w lreset# 1 0: gpio57 outputs 0 when in output mode. 1: gpio57 outputs 1 when in output mode. 6 gpio56_data r/w lreset# 1 0: gpio56 outputs 0 when in output mode. 1: gpio56 outputs 1 when in output mode. 5 gpio55_data r/w lreset# 1 0: gpio55 outputs 0 when in output mode. 1: gpio55 outputs 1 when in output mode. 4 gpio54_data r/w lreset# 1 0: gpio54 outputs 0 when in output mode. 1: gpio54 outputs 1 when in output mode. 3 gpio53_data r/w lreset# 1 0: gpio53 outputs 0 when in output mode. 1: gpio53 outputs 1 when in output mode. 2 gpio52_data r/w lreset# 1 0: gpio52 outputs 0 when in output mode. 1: gpio52 outputs 1 when in output mode. 1 gpio51_data r/w lreset# 1 0: gpio51 outputs 0 when in output mode. 1: gpio51 outputs 1 when in output mode. 0 gpio50_data r/w lreset# 1 0: gpio50 outputs 0 when in output mode. 1: gpio50 outputs 1 when in output mode. gpio5 pin status register ? index a2h (this byte could be also read by base address + 5 ) bit name r/w reset default description 7 gpio57_st r - - the pin status of gpio57/wgate#/dsr6#/t2ex. 6 gpio56_st r - - the pin status of gpio56/hdsel#/dtr6#/t2. 5 gpio55_st r - - the pin status of gpio55/step#/cts6#/p35. 4 gpio54_st r - - the pin status of gpio54/dir#/ri6#/p34. 3 gpio53_st r - - the pin status of gpio53/wdata#/dcd6#/p33.
F81867 dec, 2011 v0.12p 161 2 gpio52_st r - - the pin status of gp io52/drva#/sout6/p32. 1 gpio51_st r - - the pin status of gpio51/moa#/sin6/p31. 0 gpio50_st r - - the pin status of gp io50/densel#/rts6#/p30. gpio5 drive enable register ? index a3h bit name r/w reset default description 7 gpio57_drv_en r/w lreset# 0 gpio57 drive enable. 0: gpio57 is open drain. 1: gpio57 is push pull. 6 gpio56_drv_en r/w lreset# 0 gpio56 drive enable. 0: gpio56 is open drain. 1: gpio56 is push pull. 5 gpio55_drv_en r/w lreset# 0 gpio55 drive enable. 0: gpio55 is open drain. 1: gpio55 is push pull. 4 gpio54_drv_en r/w lreset# 0 gpio54 drive enable. 0: gpio54 is open drain. 1: gpio54 is push pull. 3 gpio53_drv_en r/w lreset# 0 gpio53 drive enable. 0: gpio53 is open drain. 1: gpio53 is push pull. 2 gpio52_drv_en r/w lreset# 0 gpio52 drive enable. 0: gpio52 is open drain. 1: gpio52 is push pull. 1 gpio51_drv_en r/w lreset# 0 gpio51 drive enable. 0: gpio51 is open drain. 1: gpio51 is push pull. 0 gpio50_drv_en r/w lreset# 0 gpio50 drive enable. 0: gpio50 is open drain. 1: gpio50 is push pull. gpio5 smi enable register ? index a8h bit name r/w reset default description 7 gpio57_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio57_smi_st is set. 6 gpio56_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio56_smi_st is set. 5 gpio55_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio55_smi_st is set. 4 gpio54_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio54_smi_st is set. 3 gpio53_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio53_smi_st is set. 2 gpio52_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio52_smi_st is set.
F81867 dec, 2011 v0.12p 162 1 gpio51_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio51_smi_st is set. 0 gpio50_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio50_smi_st is set. gpio5 smi status register ? index a9h bit name r/w reset default description 7 gpio57_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio57 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 6 gpio56_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio56 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 5 gpio55_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio55 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 4 gpio54_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio54 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 3 gpio53_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio53 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 2 gpio52_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio52 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 1 gpio51_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio51 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 0 gpio50_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio50 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 7.7.10 gpio6x configuration registers register 0x[hex] register name default value msb lsb 90 gpio6 output enable register 0 0 0 0 0 0 0 0 91 gpio6 output data register 1 1 1 1 1 1 1 1 92 gpio6 pin status register - - - - - - - - 93 gpio6 drive enable register 0 0 0 0 0 0 0 0
F81867 dec, 2011 v0.12p 163 gpio6 output enable register ? index 90h bit name r/w reset default description 7 gpio67_oe r/w lreset# 0 0: gpio67 is in input mode. 1: gpio67 is in output mode. 6 gpio66_oe r/w lreset# 0 0: gpio66 is in input mode. 1: gpio65 is in output mode. 5 gpio65_oe r/w lreset# 0 0: gpio65 is in input mode. 1: gpio65 is in output mode. 4 gpio64_oe r/w lreset# 0 0: gpio64 is in input mode. 1: gpio64 is in output mode. 3 gpio63_oe r/w lreset# 0 0: gpio63 is in input mode. 1: gpio63 is in output mode. 2 gpio62_oe r/w lreset# 0 0: gpio62 is in input mode. 1: gpio62 is in output mode. 1 gpio61_oe r/w lreset# 0 0: gpio61 is in input mode. 1: gpio61 is in output mode. 0 gpio60_oe r/w lreset# 0 0: gpio60 is in input mode. 1: gpio60 is in output mode. gpio6 output data register ? index 91h (this byte could be also written by base address + 4) bit name r/w reset default description 7 gpio67_val r/w lreset# 1 0: gpio67 outputs 0 when in output mode. 1: gpio67 outputs 1 when in output mode. 6 gpio66_val r/w lreset# 1 0: gpio66 outputs 0 when in output mode. 1: gpio66 outputs 1 when in output mode. 5 gpio65_val r/w lreset# 1 0: gpio65 outputs 0 when in output mode. 1: gpio65 outputs 1 when in output mode. 4 gpio64_val r/w lreset# 1 0: gpio64 outputs 0 when in output mode. 1: gpio64 outputs 1 when in output mode. 3 gpio63_val r/w lreset# 1 0: gpio63 outputs 0 when in output mode. 1: gpio63 outputs 1 when in output mode. 2 gpio62_val r/w lreset# 1 0: gpio62 outputs 0 when in output mode. 1: gpio62 outputs 1 when in output mode. 1 gpio61_val r/w lreset# 1 0: gpio61 outputs 0 when in output mode. 1: gpio61 outputs 1 when in output mode. 0 gpio60_val r/w lreset# 1 0: gpio60 outputs 0 when in output mode. 1: gpio60 outputs 1 when in output mode. gpio6 pin status register ? index 92h (this byte could be also read by base address + 4) bit name r/w reset default description 7 gpio67_in r - - the pin status of s5#/gpio67. 6 gpio66_in r - - the pin status of dpwrok/gpio66. 5 gpio65_in r - - the pin status of pme#/gpio65. 4 gpio64_in r - - the pin status of gpio64/dskchg#/dsr5#. 3 gpio63_in r - - the pin status of gpio63/wpt#/dtr5#/pwm3.
F81867 dec, 2011 v0.12p 164 2 gpio62_in r - - the pin status of gpio62/index#/cts5#/pwm2. 1 gpio61_in r - - the pin status of gpio61/trk0#/ri5#/pwm1. 0 gpio60_in r - - the pin status of gpio60/rdata#/dcd5#/pwm0. gpio6 drive enable register ? index 93h bit name r/w reset default description 7 gpio67_drv_en r/w lreset# 0 0: gpio67 is open drain in output mode. 1: reserved. 6 gpio66_drv_en r/w lreset# 0 0: gpio66 is open drain in output mode. 1: gpio66 is push pull in output mode. 5 gpio65_drv_en r/w lreset# 0 0: gpio65 is open drain in output mode. 1: gpio65 is push pull in output mode. 4 gpio64_drv_en r/w lreset# 0 0: gpio64 is open drain in output mode. 1: gpio64 is push pull in output mode. 3 gpio63_drv_en r/w lreset# 0 0: gpio63 is open drain in output mode. 1: gpio63 is push pull in output mode. 2 gpio62_drv_en r/w lreset# 0 0: gpio62 is open drain in output mode. 1: gpio62 is push pull in output mode. 1 gpio61_drv_en r/w lreset# 0 0: gpio61 is open drain in output mode. 1: gpio61 is push pull in output mode. 0 gpio60_drv_en r/w lreset# 0 0: gpio60 is open drain in output mode. 1: gpio60 is push pull in output mode. 7.7.11 gpio7x configuration registers register 0x[hex] register name default value msb lsb 80 gpio7 output enable register 0 0 0 0 0 0 0 0 81 gpio7 output data register 1 1 1 1 1 1 1 1 82 gpio7 pin status register - - - - - - - - 83 gpio7 drive enable register 0 0 0 0 0 0 0 0 gpio7 output enable register ? index 80h bit name r/w reset default description 7 gpio77_oe r/w lreset# 0 0: gpio77 is in input mode. 1: gpio77 is in output mode. 6 gpio76_oe r/w lreset# 0 0: gpio76 is in input mode. 1: gpio75 is in output mode. 5 gpio75_oe r/w lreset# 0 0: gpio75 is in input mode. 1: gpio75 is in output mode. 4 gpio74_oe r/w lreset# 0 0: gpio74 is in input mode. 1: gpio74 is in output mode. 3 gpio73_oe r/w lreset# 0 0: gpio73 is in input mode. 1: gpio73 is in output mode.
F81867 dec, 2011 v0.12p 165 2 gpio72_oe r/w lreset# 0 0: gpio72 is in input mode. 1: gpio72 is in output mode. 1 gpio71_oe r/w lreset# 0 0: gpio71 is in input mode. 1: gpio71 is in output mode. 0 gpio70_oe r/w lreset# 0 0: gpio70 is in input mode. 1: gpio70 is in output mode. gpio7 output data register ? index 81h (this byte could be also written by base address + 3) bit name r/w reset default description 7 gpio77_val r/w lreset# 1 0: gpio77 outputs 0 when in output mode. 1: gpio77 outputs 1 when in output mode. 6 gpio76_val r/w lreset# 1 0: gpio76 outputs 0 when in output mode. 1: gpio76 outputs 1 when in output mode. 5 gpio75_val r/w lreset# 1 0: gpio75 outputs 0 when in output mode. 1: gpio75 outputs 1 when in output mode. 4 gpio74_val r/w lreset# 1 0: gpio74 outputs 0 when in output mode. 1: gpio74 outputs 1 when in output mode. 3 gpio73_val r/w lreset# 1 0: gpio73 outputs 0 when in output mode. 1: gpio73 outputs 1 when in output mode. 2 gpio72_val r/w lreset# 1 0: gpio72 outputs 0 when in output mode. 1: gpio72 outputs 1 when in output mode. 1 gpio71_val r/w lreset# 1 0: gpio71 outputs 0 when in output mode. 1: gpio71 outputs 1 when in output mode. 0 gpio70_val r/w lreset# 1 0: gpio70 outputs 0 when in output mode. 1: gpio70 outputs 1 when in output mode. gpio7 pin status register ? index 82h (this byte could be also read by base address + 3) bit name r/w reset default description 7 gpio77_in r - - the pin status of gpio77/stb#. 6 gpio76_in r - - the pin status of gpio76/afd#. 5 gpio75_in r - - the pin status of gpio75/err#. 4 gpio74_in r - - the pin status of gpio74/init#. 3 gpio73_in r - - the pin status of gpio73/slin#. 2 gpio72_in r - - the pin status of gpio72/ack#. 1 gpio71_in r - - the pin status of gpio71/busy. 0 gpio70_in r - - the pin status of gpio70/pe/fanctrl3/pwm_dc3. gpio7 drive enable register ? index 83h bit name r/w reset default description 7 gpio77_drv_en r/w lreset# 0 0: gpio77 is open drain in output mode. 1: gpio77 is push pull in output mode. 6 gpio76_drv_en r/w lreset# 0 0: gpio76 is open drain in output mode. 1: gpio76 is push pull in output mode.
F81867 dec, 2011 v0.12p 166 5 gpio75_drv_en r/w lreset# 0 0: gpio75 is open drain in output mode. 1: gpio75 is push pull in output mode. 4 gpio74_drv_en r/w lreset# 0 0: gpio74 is open drain in output mode. 1: gpio74 is push pull in output mode. 3 gpio73_drv_en r/w lreset# 0 0: gpio73 is open drain in output mode. 1: gpio73 is push pull in output mode. 2 gpio72_drv_en r/w lreset# 0 0: gpio72 is open drain in output mode. 1: gpio72 is push pull in output mode. 1 gpio71_drv_en r/w lreset# 0 0: gpio71 is open drain in output mode. 1: gpio71 is push pull in output mode. 0 gpio70_drv_en r/w lreset# 0 0: gpio70 is open drain in output mode. 1: gpio70 is push pull in output mode. 7.7.12 gpio8x configuration registers register 0x[hex] register name default value msb lsb 88 gpio8 output enable register 0 0 0 0 0 0 0 0 89 gpio8 output data register 1 1 1 1 1 1 1 1 8a gpio8 pin status register - - - - - - - - 8b gpio8 drive enable register 0 0 0 0 0 0 0 0 8e gpio8 smi enable register 0 0 0 0 0 0 0 0 8f gpio8 smi status register 0 0 0 0 0 0 0 0 gpio8 output enable register ? index 88h bit name r/w reset default description 7 gpio87_oe r/w lreset# 0 0: gpio87 is in input mode. 1: gpio87 is in output mode. 6 gpio86_oe r/w lreset# 0 0: gpio86 is in input mode. 1: gpio85 is in output mode. 5 gpio85_oe r/w lreset# 0 0: gpio85 is in input mode. 1: gpio85 is in output mode. 4 gpio84_oe r/w lreset# 0 0: gpio84 is in input mode. 1: gpio84 is in output mode. 3 gpio83_oe r/w lreset# 0 0: gpio83 is in input mode. 1: gpio83 is in output mode. 2 gpio82_oe r/w lreset# 0 0: gpio82 is in input mode. 1: gpio82 is in output mode. 1 gpio81_oe r/w lreset# 0 0: gpio81 is in input mode. 1: gpio81 is in output mode. 0 gpio80_oe r/w lreset# 0 0: gpio80 is in input mode. 1: gpio80 is in output mode.
F81867 dec, 2011 v0.12p 167 gpio8 output data register ? index 89h (this byte could be also written by base address + 2) bit name r/w reset default description 7 gpio87_val r/w lreset# 1 0: gpio87 outputs 0 when in output mode. 1: gpio87 outputs 1 when in output mode. 6 gpio86_val r/w lreset# 1 0: gpio86 outputs 0 when in output mode. 1: gpio86 outputs 1 when in output mode. 5 gpio85_val r/w lreset# 1 0: gpio85 outputs 0 when in output mode. 1: gpio85 outputs 1 when in output mode. 4 gpio84_val r/w lreset# 1 0: gpio84 outputs 0 when in output mode. 1: gpio84 outputs 1 when in output mode. 3 gpio83_val r/w lreset# 1 0: gpio83 outputs 0 when in output mode. 1: gpio83 outputs 1 when in output mode. 2 gpio82_val r/w lreset# 1 0: gpio82 outputs 0 when in output mode. 1: gpio82 outputs 1 when in output mode. 1 gpio81_val r/w lreset# 1 0: gpio81 outputs 0 when in output mode. 1: gpio81 outputs 1 when in output mode. 0 gpio80_val r/w lreset# 1 0: gpio80 outputs 0 when in output mode. 1: gpio80 outputs 1 when in output mode. gpio8 pin status register ? index 8ah (this byte could be also read by base address + 2) bit name r/w reset default description 7 gpio87_in r - - the pin status of gpio87/pd7. 6 gpio86_in r - - the pin status of gpio86/pd6. 5 gpio85_in r - - the pin status of gpio85/pd5. 4 gpio84_in r - - the pin status of gpio84/pd4. 3 gpio83_in r - - the pin status of gpio83/pd3. 2 gpio82_in r - - the pin status of gpio82/pd2. 1 gpio81_in r - - the pin status of gpio81/pd1. 0 gpio80_in r - - the pin status of gpio80/pd0. gpio8 drive enable register ? index 8bh bit name r/w reset default description 7 gpio87_drv_en r/w lreset# 0 0: gpio87 is open drain in output mode. 1: gpio87 is push pull in output mode. 6 gpio86_drv_en r/w lreset# 0 0: gpio86 is open drain in output mode. 1: gpio86 is push pull in output mode. 5 gpio85_drv_en r/w lreset# 0 0: gpio85 is open drain in output mode. 1: gpio85 is push pull in output mode. 4 gpio84_drv_en r/w lreset# 0 0: gpio84 is open drain in output mode. 1: gpio84 is push pull in output mode. 3 gpio83_drv_en r/w lreset# 0 0: gpio83 is open drain in output mode. 1: gpio83 is push pull in output mode. 2 gpio82_drv_en r/w lreset# 0 0: gpio82 is open drain in output mode. 1: gpio82 is push pull in output mode.
F81867 dec, 2011 v0.12p 168 1 gpio81_drv_en r/w lreset# 0 0: gpio81 is open drain in output mode. 1: gpio81 is push pull in output mode. 0 gpio80_drv_en r/w lreset# 0 0: gpio80 is open drain in output mode. 1: gpio80 is push pull in output mode. gpio8 smi enable register ? index 8eh bit name r/w reset default description 7 gpio87_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio87_smi_st is set. 6 gpio86_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio86_smi_st is set. 5 gpio85_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio85_smi_st is set. 4 gpio84_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio84_smi_st is set. 3 gpio83_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio83_smi_st is set. 2 gpio82_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio82_smi_st is set. 1 gpio81_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio81_smi_st is set. 0 gpio80_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio80_smi_st is set. gpio8 smi status register ? index 8fh bit name r/w reset default description 7 gpio87_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio87 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 6 gpio86_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio86 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 5 gpio85_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio85 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 4 gpio84_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio84 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 3 gpio83_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio83 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 2 gpio82_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio82 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status.
F81867 dec, 2011 v0.12p 169 1 gpio81_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio81 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 0 gpio80_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio80 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 7.8 gpio8x scan code registers register 0x[hex] register name default value msb lsb d8 gpio8 make code 0 register 0 0 0 0 0 0 0 0 d9 gpio8 make code 1 register 0 0 0 0 0 0 0 0 da gpio8 make code 2 register 0 0 0 0 0 0 0 0 db gpio8 make code 3 register 0 0 0 0 0 0 0 0 dc gpio8 make code 4 register 0 0 0 0 0 0 0 0 dd gpio8 make code 5 register 0 0 0 0 0 0 0 0 de gpio8 make code 6 register 0 0 0 0 0 0 0 0 df gpio8 make code 7 register 0 0 0 0 0 0 0 0 c8 gpio8 pre code 0 register 1 1 1 0 0 0 0 0 c9 gpio8 pre code 1 register 1 1 1 0 0 0 0 0 ca gpio8 pre code 2 register 1 1 1 0 0 0 0 0 cb gpio8 pre code 3 register 1 1 1 0 0 0 0 0 cc gpio8 pre code 4 register 1 1 1 0 0 0 0 0 cd gpio8 pre code 5 register 1 1 1 0 0 0 0 0 ce gpio8 pre code 6 register 1 1 1 0 0 0 0 0 cf gpio8 pre code 7 register 1 1 1 0 0 0 0 0 b8 gpio8 scan code 0 control register 0 0 0 0 0 0 0 0 b9 gpio8 scan code 1 control register 0 0 0 0 0 0 0 0 ba gpio8 scan code 2 control register 0 0 0 0 0 0 0 0 bb gpio8 scan code 3 control register 0 0 0 0 0 0 0 0 bc gpio8 scan code 4 control register 0 0 0 0 0 0 0 0 bd gpio8 scan code 5 control register 0 0 0 0 0 0 0 0 be gpio8 scan code 6 control register 0 0 0 0 0 0 0 0 bf gpio8 scan code 7 control register 0 0 0 0 0 0 0 0 ac-ad reserved for fintek. 0 0 0 0 0 0 0 0 ae gpio8 function select 1 register 0 0 0 0 0 0 0 0 af gpio8 function select 2 register 0 0 0 0 0 0 0 0
F81867 dec, 2011 v0.12p 170 gpio8 make code 0 register ? index d8h bit name r/w reset default description 7-0 gp_make_code0 r/w 5vsb 0 this byte is used to assert the make code when the scan code event 0 is occurred. the scan code events will set kbc obf and put their make/break code into the kbc output buffer. the break code is make code + 0x80 and this function is implemented by c. the source of event is gpio80. gpio8 make code 1 register ? index d9h bit name r/w reset default description 7-0 gp_make_code1 r/w 5vsb 0 this byte is used to assert the make code when the scan code event 0 is occurred. the scan code events will set kbc obf and put their make/break code into the kbc output buffer. the break code is make code + 0x80 and this function is implemented by cthe source of event is gpio81. gpio8 make code 2 register ? index dah bit name r/w reset default description 7-0 gp_make_code2 r/w 5vsb 0 this byte is used to assert the make code when the scan code event 0 is occurred. the scan code events will set kbc obf and put their make/break code into the kbc output buffer. the break code is make code + 0x80 and this function is implemented by c the source of event is gpio82. gpi8o make code 3 register ? index dbh bit name r/w reset default description 7-0 gp_make_code3 r/w 5vsb 0 this byte is used to assert the make code when the scan code event 0 is occurred. the scan code events will set kbc obf and put their make/break code into the kbc output buffer. the break code is make code + 0x80 and this function is implemented by c. the source of event is gpio83. gpio8 make code 4 register ? index dch bit name r/w reset default description 7-0 gp_make_code4 r/w 5vsb 0 this byte is used to assert the make code when the scan code event 0 is occurred. the scan code events will set kbc obf and put their make/break code into the kbc output buffer. the break code is make code + 0x80 and this function is implemented by c. the source of event is gpio84. gpio8 make code 5 register ? index ddh bit name r/w reset default description 7-0 gp_make_code5 r/w 5vsb 0 this byte is used to assert the make code when the scan code event 0 is occurred. the scan code events will set kbc obf and put their make/break code into the kbc output buffer. the break code is make code + 0x80 and this function is implemented by c. the source of event is gpio85. gpio make code 6 register ? index deh bit name r/w reset default description 7-0 gp_make_code6 r/w 5vsb 0 this byte is used to assert the make code when the scan code event 0 is occurred. the scan code events will set kbc obf and put their make/break code into the kbc output buffer. the break code is make code + 0x80 and this function is implemented by c. the source of event is gpio86.
F81867 dec, 2011 v0.12p 171 gpio8 make code 7 register ? index dfh bit name r/w reset default description 7-0 gp_make_code7 r/w 5vsb 0 this byte is used to assert the make code when the scan code event 0 is occurred. the scan code events will set kbc obf and put their make/break code into the kbc output buffer. the break code is make code + 0x80 and this function is implemented by c. the source of event is gpio87. gpio8 pre-code 0 register ? index c8h bit name r/w reset default description 7-0 gp_pre_code0 r/w 5vsb 0xe0 this byte is used to assert the pre-code before the make/break code when it is enabled. gpio8 pre-code 1 register ? index c9h bit name r/w reset default description 7-0 gp_pre_code1 r/w 5vsb 0xe0 this byte is used to assert the pre-code before the make/break code when it is enabled. gpio8 pre-code 2 register ? index cah bit name r/w reset default description 7-0 gp_pre_code2 r/w 5vsb 0xe0 this byte is used to assert the pre-code before the make/break code when it is enabled. gpio8 pre-code 3 register ? index cbh bit name r/w reset default description 7-0 gp_pre_code3 r/w 5vsb 0xe0 this byte is used to assert the pre-code before the make/break code when it is enabled. gpio8 pre-code 4 register ? index cch bit name r/w reset default description 7-0 gp_pre_code4 r/w 5vsb 0xe0 this byte is used to assert the pre-code before the make/break code when it is enabled. gpio8 pre-code 5 register ? index cdh bit name r/w reset default description 7-0 gp_pre_code5 r/w 5vsb 0xe0 this byte is used to assert the pre-code before the make/break code when it is enabled. gpio8 pre-code 6 register ? index ceh bit name r/w reset default description 7-0 gp_pre_code6 r/w 5vsb 0xe0 this byte is used to assert the pre-code before the make/break code when it is enabled. gpio8 pre-code 7 register ? index cfh bit name r/w reset default description 7-0 gp_pre_code7 r/w 5vsb 0xe0 this byte is used to assert the pre-code before the make/break code when it is enabled.
F81867 dec, 2011 v0.12p 172 gpio8 scan code 0 control register ? index b8h bit name r/w reset default description 7 gp0_ctrl_en r/w 5vsb 0 set ?1? will assert a left ?ctrl? key code first when the scan code event is occurred. 6 gp0_alt_en r/w 5vsb 0 set ?1? will assert a left ?alt? key code first when the scan code event is occurred. 5 gp0_shift_en r/w 5vsb 0 set ?1? will assert a left ?shift? key code first when the scan code event is occurred. 4 gp0_pre_en r/w 5vsb 0 set ?1? will assert a left pre-code first when scan code 0 event is occurred. when multiple keys are enabled, the sequence is ?ctrl? ? ?alt? ? ?shift? ? pre-code ? make/break code. 3-2 gp0_delay_time r/w 5vsb 0 the delay time for repeating the make code could be user defined. c read this register to determine the delay time. 0 gp0_rep_time r/w 5vsb 0 the repeat time for repeating the ma ke code could be user defined. c read this register to determine the delay time. gpio8 scan code 1 control register ? index b9h bit name r/w reset default description 7 gp1_ctrl_en r/w 5vsb 0 set ?1? will assert a left ?ctrl? key code first when scan code event occurred. 6 gp1_alt_en r/w 5vsb 0 set ?1? will assert a left ?alt? key code first when scan code event occurred. 5 gp1_shift_en r/w 5vsb 0 set ?1? will assert a left ?shift? key code first when scan code event occurred. 4 gp1_pre_en r/w 5vsb 0 set ?1? will assert a left pre-code first when scan code 0 event occurred. when multiple keys are enabled, the sequence is ?ctrl? ? ?alt? ? ?shift? ? pre-code ? make/break code. 3-2 gp1_delay_time r/w 5vsb 0 the delay time for repeating the make code could be user defined. c read this register to determine the delay time. 0 gp1_rep_time r/w 5vsb 0 the repeat time for repeating the ma ke code could be user defined. c read this register to determine the delay time. gpio8 scan code 2 control register ? index bah bit name r/w reset default description 7 gp2_ctrl_en r/w 5vsb 0 set ?1? will assert a left ?ctrl? key code first when scan code event occurred. 6 gp2_alt_en r/w 5vsb 0 set ?1? will assert a left ?alt? key code first when scan code event occurred. 5 gp2_shift_en r/w 5vsb 0 set ?1? will assert a left ?shift? key code first when scan code event occurred. 4 gp2_pre_en r/w 5vsb 0 set ?1? will assert a left pre-code first when scan code 0 event occurred. when multiple keys are enabled, the sequence is ?ctrl? ? ?alt? ? ?shift? ? pre-code ? make/break code. 3-2 gp2_delay_time r/w 5vsb 0 the delay time for repeating the make code could be user defined. c read this register to determine the delay time. 0 gp2_rep_time r/w 5vsb 0 the repeat time for repeating the ma ke code could be user defined. c read this register to determine the delay time. gpio8 scan code 3 control register ? index bbh bit name r/w reset default description 7 gp3_ctrl_en r/w 5vsb 0 set ?1? will assert a left ?ctrl? key code first when scan code event occurred. 6 gp3_alt_en r/w 5vsb 0 set ?1? will assert a left ?alt? key code first when scan code event occurred. 5 gp3_shift_en r/w 5vsb 0 set ?1? will assert a left ?shift? key code first when scan code event occurred.
F81867 dec, 2011 v0.12p 173 4 gp3_pre_en r/w 5vsb 0 set ?1? will assert a left pre-code first when scan code 0 event occurred. when multiple keys are enabled, the sequence is ?ctrl? ? ?alt? ? ?shift? ? pre-code ? make/break code. 3-2 gp3_delay_time r/w 5vsb 0 the delay time for repeating the make code could be user defined. c read this register to determine the delay time. 0 gp3_rep_time r/w 5vsb 0 the repeat time for repeating the ma ke code could be user defined. c read this register to determine the delay time. gpio8 scan code 4 control register ? index bch bit name r/w reset default description 7 gp4_ctrl_en r/w 5vsb 0 set ?1? will assert a left ?ctrl? key code first when scan code event occurred. 6 gp4_alt_en r/w 5vsb 0 set ?1? will assert a left ?alt? key code first when scan code event occurred. 5 gp4_shift_en r/w 5vsb 0 set ?1? will assert a left ?shift? key code first when scan code event occurred. 4 gp4_pre_en r/w 5vsb 0 set ?1? will assert a left pre-code first when scan code 0 event occurred. when multiple keys are enabled, the sequence is ?ctrl? ? ?alt? ? ?shift? ? pre-code ? make/break code. 3-2 gp4_delay_time r/w 5vsb 0 the delay time for repeating the make code could be user defined. c read this register to determine the delay time. 0 gp4_rep_time r/w 5vsb 0 the repeat time for repeating the ma ke code could be user defined. c read this register to determine the delay time. gpio8 scan code 5 control register ? index bdh bit name r/w reset default description 7 gp5_ctrl_en r/w 5vsb 0 set ?1? will assert a left ?ctrl? key code first when scan code event occurred. 6 gp5_alt_en r/w 5vsb 0 set ?1? will assert a left ?alt? key code first when scan code event occurred. 5 gp5_shift_en r/w 5vsb 0 set ?1? will assert a left ?shift? key code first when scan code event occurred. 4 gp5_pre_en r/w 5vsb 0 set ?1? will assert a left pre-code first when scan code 0 event occurred. when multiple keys are enabled, the sequence is ?ctrl? ? ?alt? ? ?shift? ? pre-code ? make/break code. 3-2 gp5_delay_time r/w 5vsb 0 the delay time for repeating the make code could be user defined. c read this register to determine the delay time. 0 gp5_rep_time r/w 5vsb 0 the repeat time for repeating the ma ke code could be user defined. c read this register to determine the delay time. gpio8 scan code 6 control register ? index beh bit name r/w reset default description 7 gp6_ctrl_en r/w 5vsb 0 set ?1? will assert a left ?ctrl? key code first when scan code event occurred. 6 gp6_alt_en r/w 5vsb 0 set ?1? will assert a left ?alt? key code first when scan code event occurred. 5 gp6_shift_en r/w 5vsb 0 set ?1? will assert a left ?shift? key code first when scan code event occurred. 4 gp6_pre_en r/w 5vsb 0 set ?1? will assert a left pre-code first when scan code 0 event occurred. when multiple keys are enabled, the sequence is ?ctrl? ? ?alt? ? ?shift? ? pre-code ? make/break code. 3-2 gp6_delay_time r/w 5vsb 0 the delay time for repeating the make code could be user defined. c read this register to determine the delay time. 0 gp6_rep_time r/w 5vsb 0 the repeat time for repeating the ma ke code could be user defined. c read this register to determine the delay time.
F81867 dec, 2011 v0.12p 174 gpio8 scan code 7 control register ? index bfh bit name r/w reset default description 7 gp7_ctrl_en r/w 5vsb 0 set ?1? will assert a left ?ctrl? key code first when scan code event occurred. 6 gp7_alt_en r/w 5vsb 0 set ?1? will assert a left ?alt? key code first when scan code event occurred. 5 gp7_shift_en r/w 5vsb 0 set ?1? will assert a left ?shift? key code first when scan code event occurred. 4 gp7_pre_en r/w 5vsb 0 set ?1? will assert a left pre-code first when scan code 0 event occurred. when multiple keys are enabled, the sequence is ?ctrl? ? ?alt? ? ?shift? ? pre-code ? make/break code. 3-2 gp7_delay_time r/w 5vsb 0 the delay time for repeating the make code could be user defined. c read this register to determine the delay time. 0 gp7_rep_time r/w 5vsb 0 the repeat time for repeating the ma ke code could be user defined. c read this register to determine the delay time. gpio8 function select 1 register ? index aeh bit name r/w reset default description 7-6 gpio83_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio83 is. 5-4 gpio82_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio82 is. 3-2 gpio81_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio81 is. 1-0 gpio80_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio80 is. gpio8 function select 2 register ? index afh bit name r/w reset default description 7-6 gpio87_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio87 is. 5-4 gpio86_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio86 is. 3-2 gpio85_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio85 is. 1-0 gpio84_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio84 is. remark: gpio also provides index/data port to access the whole gp io registers. the index port is base address + 0 and data port is base address + 1. the index for each register is the same as the one for configuration register. for example, to write gpio0 output enable re gister 0xaa, below is the procedure: 1. write index port 0xf0. 2. write data port 0xaa.
F81867 dec, 2011 v0.12p 175 7.9 wdt registers (cr07) ?-? reserved or tri-state register 0x[hex] register name default value msb lsb 30 wdt device enable register - - - - - - - 0 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 0 0 0 0 0 0 0 f5 wdt control register 0 0 0 0 0 0 0 0 f6 wdt timer register 0 0 0 0 0 0 0 0 fa wdt pme enable register 0 0 0 1 - - - 0 wdt device base address enable register ? index 30h bit name r/w reset default description 7-1 reserved - - 0 reserved 0 wdt_en r/w 5vsb 0 0: disable wdt base address. 1: enable wdt base address. base address high register ? index 60h bit name r/w reset default description 7-0 base_addr_hi r/w 5vsb 00h the msb of wdt base address. base address low register ? index 61h bit name r/w reset default description 7-0 base_addr_lo r/w 5vsb 00h the lsb of wdt base address. watchdog control configuration register 1 ? index f5h bit name r/w reset default description 7 reserved r - 0 reserved 6 wdtmout_sts r/w 5vsb 0 if watchdog timeout event occurred, this bi t will be set to 1. write a 1 to this bit will clear it to 0. 5 wd_en r/w 5vsb 0 if this bit is set to 1, the counting of watchdog time is enabled. 4 wd_pulse r/w 5vsb 0 select output mode (0: level, 1: pulse) of rstout# by setting this bit. 3 wd_unit r/w 5vsb 0 select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit. 2 wd_hactive r/w 5vsb 0 select output polarity of rstout# (1: high active, 0: low active) by setting this bit. 1-0 wd_pswidth r/w 5vsb 0 select output pulse width of rstout# 0: 1 ms 1: 25 ms 2: 125 ms 3: 5 sec watchdog timer configuration register 2 ? index f6h bit name r/w reset default description 7-0 wd_time r/w 5vsb 0 time of watchdog timer (0~255)
F81867 dec, 2011 v0.12p 176 watchdog pme enable configuration register 2 ? index fah bit name r/w reset default description 7 wdt_pme r 5vsb 0 0: no wdt pme occurred. 1: wdt pme occurred. the wdt pme is occurred one unit before wdt timeout. 6 wdt_pme_en r/w 5vsb 0 0: disable watchdog pme. 1: enable watchdog pme. 5 reserved r - 0 reserved 4 wdt_clk_sel r/w 5vsb 1 wdt clock source select 0: internal 1khz clock. 1: 1khz clock driven by clkin. 3-1 reserved r - 0 reserved 0 wdout_en r/w 5vsb 0 0: disable watchdog time out output via wdtrst#. 1: enable watchdog time out output via wdtrst#. 7.10 pme, acpi and eup registers (ldn 0x0a) ?-? reserved or tri-state register 0x[hex] register name default value msb lsb 30 pme device enable register - - - - - - - 0 f0 pme event enable 1 register 0 0 0 0 0 0 0 0 f1 pme event status 1 register - - - - - - - - f2 pme event enable 2 register 0 0 0 0 0 0 0 0 f3 pme event status 2 register - - - - - - - - f4 acpi control register 1 - - 0 0 0 1 1 1 f5 acpi control register 2 - 0 0 1 1 1 - - f6 acpi control register 3 0 - - 0 0 - - - f8 led control register 1 - 0 0 0 0 0 0 0 f9 led control register 2 - 0 0 0 - 0 0 0 fa led control register 3 - - - - 0 1 1 1 fc dsw delay register - - - - - - 0 0 fe ri de-bounce select register 0 0- - - - - 0 0 e0 erp enable register - - 0 0 1 1 0 0 e1 erp control register 1 1 0 0 0 0 0 0 - e2 erp control register 2 - 0 0 0 0 0 0 0 e3 erp pwsin de-bounce register 0 0 0 1 0 0 1 1 e4 erp rsmrst de-bounce register 0 0 0 0 1 0 0 1 e5 erp pwsout pulse register 1 1 0 0 0 1 1 1 e6 erp pson de-bounce register 0 0 0 1 0 0 1 1 e7 erp deep s5 delay register 0 1 1 0 0 0 1 1 e8 erp wakeup enable register 0 - 0 1 0 0 0 0
F81867 dec, 2011 v0.12p 177 e9 erp deep s3 delay register 0 0 0 0 1 1 1 1 ec erp mode select register 0 0 0 1 0 1 - - ed erp wdt control register - - - - - - 0 0 ee erp wdt time register 0 0 0 0 0 0 0 0 pme device enable register ? index 30h bit name r/w reset default description 7-1 reserved - - - reserved 0 pme_en r/w 5vsb 0 pme global enable register. 0: disable pme. 1: enable pme. pme event enable 1 register ? index f0h bit name r/w reset default description 7 reserved - - - reserved 6 wdt_pme_en r/w 5vsb 0 wdt pme event enable. 0: disable wdt pme event. 1: enable wdt pme event. 5 gp_pme_en r/w 5vsb 0 gpio pme event enable. 0: disable gpio pme event. 1: enable gpio pme event. 4 mo_pme_en r/w 5vsb 0 mouse pme event enable. 0: disable mouse pme event. 1: enable mouse pme event. 3 kb_pme_en r/w 5vsb 0 keyboard pme event enable. 0: disable keyboard pme event. 1: enable keyboard pme event. 2 hm_pme_en r/w 5vsb 0 hardware monitor pme event enable. 0: disable hardware monitor pme event. 1: enable hardware monitor pme event. 1 prt_pme_en r/w 5vsb 0 parallel port pme event enable. 0: disable parallel port pme event. 1: enable parallel port pme event. 0 fdc_pme_en r/w 5vsb 0 fdc pme event enable. 0: disable fdc pme event. 1: enable fdc pme event. pme event status 1 register ? index f1h bit name r/w reset default description 7 erp_pme_st r/wc 5vsb - erp pme event status. 0: erp has no pme event. 1: erp has a pme event to assert. write 1 to clear to be ready for next pme event.
F81867 dec, 2011 v0.12p 178 6 wdt_pme_st r/wc 5vsb - wdt pme event status. 0: wdt has no pme event. 1: wdt has a pme event to assert. write 1 to clear to be ready for next pme event. 5 gp_pme_st r/wc 5vsb - gpio pme event status. 0: gpio has no pme event. 1: gpio has a pme event to assert. write 1 to clear to be ready for next pme event. 4 mo_pme_st r/wc 5vsb - mouse pme event status. 0: mouse has no pme event. 1: mouse has a pme event to assert. wr ite 1 to clear to be ready for next pme event. 3 kb_pme_st r/wc 5vsb - keyboard pme event status. 0: keyboard has no pme event. 1: keyboard has a pme event to assert. write 1 to clear to be ready for next pme event. 2 hm_pme_st r/wc 5vsb - hardware monitors pme event status. 0: hardware monitor has no pme event. 1: hardware monitor has a pme event to assert. write 1 to clear to be ready for next pme event. 1 prt_pme_st r/wc 5vsb - parallel port pme event status. 0: parallel port has no pme event. 1: parallel port has a pme event to assert. write 1 to clear to be ready for next pme event. 0 fdc_pme_st r/wc 5vsb - fdc pme event status. 0: fdc has no pme event. 1: fdc has a pme event to assert. write 1 to clear to be ready for next pme event. pme event enable 2 register ? index f2h bit name r/w reset default description 7 ri2_pme_en r/w 5vsb 0 ri2# pme event enable. 0: disable ri2# pme event. 1: enable ri2# pme event. 6 ri1_pme_en r/w 5vsb 0 ri1# pme event enable. 0: disable ri1# pme event. 1: enable ri1# pme event. 5 uart6_pme_en r/w 5vsb 0 uart 6 pme event enable. 0: disable uart 6 pme event. 1: enable uart 6 pme event. 4 uart5_pme_en r/w 5vsb 0 uart 5 pme event enable. 0: disable uart 5 pme event. 1: enable uart 5 pme event.
F81867 dec, 2011 v0.12p 179 3 uart4_pme_en r/w 5vsb 0 uart 4 pme event enable. 0: disable uart 4 pme event. 1: enable uart 4 pme event. 2 uart3_pme_en r/w 5vsb 0 uart 3 pme event enable. 0: disable uart 3 pme event. 1: enable uart 3 pme event. 1 uart2_pme_en r/w 5vsb 0 uart 2 pme event enable. 0: disable uart 2 pme event. 1: enable uart 2 pme event. 0 uart1_pme_en r/w 5vsb 0 uart 1 pme event enable. 0: disable uart 1 pme event. 1: enable uart 1 pme event. pme event status 2 register ? index f3h bit name r/w reset default description 7 ri2_pme_st r/wc 5vsb - ri2# pme event status. 0: ri2# has no pme event. 1: ri2# has a pme event to assert. writ e 1 to clear to be ready for next pme event. 6 ri1_pme_st r/wc 5vsb - ri1# pme event status. 0: ri1# has no pme event. 1: ri1# has a pme event to assert. writ e 1 to clear to be ready for next pme event. 5 uart6_pme_st r/wc 5vsb - uart 6 pme event status. 0: uart 6 has no pme event. 1: uart 6 has a pme event to assert. write 1 to clear to be ready for next pme event. 4 uart5_pme_st r/wc 5vsb - uart 5 pme event status. 0: uart 5 has no pme event. 1: uart 5 has a pme event to assert. write 1 to clear to be ready for next pme event. 3 uart4_pme_st r/wc 5vsb - uart 4 pme event status. 0: uart 4 has no pme event. 1: uart 4 has a pme event to assert. write 1 to clear to be ready for next pme event.
F81867 dec, 2011 v0.12p 180 2 uart3_pme_st r/wc 5vsb - uart 3 pme event status. 0: uart 3 has no pme event. 1: uart 3 has a pme event to assert. write 1 to clear to be ready for next pme event. 1 uart2_pme_st r/wc 5vsb - uart 2 pme event status. 0: uart 2 has no pme event. 1: uart 2 has a pme event to assert. write 1 to clear to be ready for next pme event. 0 uart1_pme_st r/wc 5vsb - uart 1 pme event status. 0: uart 1 has no pme event. 1: uart 1 has a pme event to assert. write 1 to clear to be ready for next pme event. acpi control register 1 ? index f4h bit name r/w reset default description 7-6 reserved - - - reserved. 5 en_gpwakeup r/w vbat 0 set one to enable gpio smi event asserted via pwsout#. 4 en_kbwakeup r/w vbat 0 set one to enable keyboard wake up event asserted via pwsout#. 3 en_mowakeup r/w vbat 0 set one to enable mouse wakeup event asserted via pwsout#. 2-1 pwrctrl r/w vbat 11 the acpi control the pson_n to always on or always off or keep last state 00 : keep last state 10 : always on 01 : bypass mode. 11: always off 0 vsb_pwr_loss r/w 5vsb 1 when 5vsb power lose, it will set to 1, and write 1 to clear it acpi control register 2 ? index f5h bit name r/w reset default description 7 reserved - - - reserved. 6-5 pwrok_delay r/w 5vsb 0 the additional pwrok delay. 00: no delay (default) 01: 100ms. 10: 200ms 11: 400ms. 4-3 vdd_delay r/w 5vsb 11 the pwrok delay timing from v dd3vok by followed setting 00 : 100ms 01 : 200ms 10 : 300ms 11 : 400ms (default) 2 vindb_en r/w 5vsb 1 enable the atxpg de-bounce. (10us) 1-0 reserved - - - reserved.
F81867 dec, 2011 v0.12p 181 acpi control register 3 ? index f6h bit name r/w reset default description 7 s3_sel r/w 5vsb 0 select the kbc s3 condition source. 0: enter s3 state when internal vdd3vok signal de-asserted. 1: enter s3 state when s3# is low or the ts3 register is set to 1. 6-5 reserved - 5vsb - reserved. 4 pson_del_en r/w 5vsb 0 0: pson# is the inverted of s3# signal. 1: pson# will sink low only if the time af ter the last turn-off elapse at least 4 seconds. 3 wdt_pwrok_en r/w 5vsb 0 set ?1? to this bit will enable wdt timeout event asset from pwrok pin. 2-0 reserved - - reserved. led control register 1 ? index f8h bit name r/w reset default description 7 led_vcc_inv_dis r/w vbat 0 0: led_vcc clock output is inverted. 1: led_vcc clock output is not inverted. 6 led_vcc_ds3 r/w vbat 0 0: disable led_vcc deep s3 mode. 1: enable led_vcc deep s3 mode. ou tput 75% duty 0.25hz clock. 5-4 led_vcc_s5_mode r/w vbat 00 the three bits {led_vcc_s5_mode_add, led_vcc_s5_mode [1:0]} select the led_vcc mode in s5 state. 000: sink low. 001: tri-state or drive high control by gpio11_drv_en. 010: 0.5hz clock with 50% duty. 011: 1hz clock with 50% duty. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 25% duty.* 111: 0.25hz clock with 25% duty.* *when led_vcc_inv_dis is set to ?1? the duty is 25%, otherwise, the duty is 75%. 3-2 led_vcc_s3_mode r/w vbat 00 the three bits {led_vcc_s3_mode_add, led_vcc_s3_mode [1:0]} select the led_vcc mode in s3 state. 000: sink low. 001: tri-state or drive high control by gpio11_drv_en. 010: 0.5hz clock with 50% duty. 011: 1hz clock with 50% duty. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 25% duty.* 111: 0.25hz clock with 25% duty.* *when led_vcc_inv_dis is set to ?1? the duty is 25%, otherwise, the duty is 75%.
F81867 dec, 2011 v0.12p 182 1-0 led_vcc_s0_mode r/w vbat 00 the three bits {led_vcc_s0_mode_add, led_vcc_s0_mode [1:0]} select the led_vcc mode in s0 state. 000: sink low. 001: tri-state or drive high control by gpio11_drv_en. 010: 0.5hz clock with 50% duty. 011: 1hz clock with 50% duty. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 25% duty.* 111: 0.25hz clock with 25% duty.* *when led_vcc_inv_dis is set to ?1? the duty is 25%, otherwise, the duty is 75%. led control register 2 ? index f9h bit name r/w reset default description 7 reserved - - - reserved 6 led_vsb_s5_mode_add r/w vbat 0 refer to led_vsb_s5_mode. 5 led_vsb_s3_mode_add r/w vbat 0 refer to led_vsb_s3_mode. 4 led_vsb_s0_mode_add r/w vbat 0 refer to led_vsb_s0_mode. 3 reserved - - - reserved 2 led_vcc_s5_mode_add r/w vbat 0 refer to led_vcc_s5_mode. 1 led_vcc_s3_mode_add r/w vbat 0 refer to led_vcc_s3_mode. 0 led_vcc_s0_mode_add r/w vbat 0 refer to led_vcc_s0_mode. led control register 3 ? index fah bit name r/w reset default description 7 reserved - - - reserved 6 led_vsb_ds3 r/w vbat 0 0: disable led_vsb deep s3 mode. 1: enable led_vsb deep s3 mode. output 0.25hz clock with 25% duty. 5-4 led_vsb_s5_mode r/w vbat 00 the three bits {led_vsb_s5_mode_add, led_vsb_s5_mode [1:0]} select the led_vsb mode in s5 state. 000: sink low. 001: tri-state or drive high control by gpio10_drv_en. 010: 0.5hz clock with 50% duty. 011: 1hz clock with 50% duty. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 25% duty.* 111: 0.25hz clock with 25% duty.*
F81867 dec, 2011 v0.12p 183 3-2 led_vsb_s3_mode r/w vbat 00 the three bits {led_vsb_s3_mode_add, led_vsb_s3_mode [1:0]} select the led_vsb mode in s3 state. 000: sink low. 001: tri-state or drive high control by gpio10_drv_en. 010: 0.5hz clock with 50% duty. 011: 1hz clock with 50% duty. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 25% duty.* 111: 0.25hz clock with 25% duty.* 1-0 led_vsb_s0_mode r/w vbat 00 the three bits {led_vsb_s0_mode_add, led_vsb_s0_mode [1:0]} select the led_vsb mode in s0 state. 000: sink low. 001: tri-state or drive high control by gpio10_drv_en. 010: 0.5hz clock with 50% duty. 011: 1hz clock with 50% duty. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 25% duty.* 111: 0.25hz clock with 25% duty.* dsw delay register ? index fch bit name r/w reset default description 7 e2h_pme_st r/wc - - ec to host pme event status. 0: ec to host has no pme event. 1: ec to host has a pme event to assert. write 1 to clear to be ready for next pme event. 6 cir_pme_st r/wc 5vsb - cir wakeup pme event status. 0: cir wakeup has no pme event. 1: cir wakeup a pme event to assert. write 1 to clear to be ready for next pme event. 5 e2h_pme_en r/wc - - ec to host pme event enable. 0: disable ec to host pme event. 1: enable ec to host pme event. 4 cir_pme_en r/wc 5vsb - cir event enable. 0: disable cir pme event. 1: enable cir pme event. 3-0 dsw_delay r/w 5vsb 7 this is the delay time between sus_warn# and sus_ack#. the unit is 0.5 sec. default time is 3.5s ~ 4s. the default could be trimmed to 0s ~ 0.5s.
F81867 dec, 2011 v0.12p 184 ri de-bounce select register ? index feh bit name r/w reset default description 7-2 reserved - - - reserved 1-0 ri_db_sel r/w 5vsb 0 select ri# de-bounce time. 00: reserved. 01: 200us. 10: 2ms. 11: 20ms. erp enable register ? index e0h bit name r/w reset default description 7 erp_en r/w vbat 0 0 : disable erp function 1: enable erp function 6 s3_back r/w vbat 0 this bit will set ?1? when system is back from s3 state. 5-2 reserved - - - reserved 1 ring_pme_en r/w vbat 0 ring1 pme event enable. 0: disable ring1 pme event. 1: enable ring1 pme event, when ring1 falling edge detect 0 ring_pwsout_en r/w vbat 0 ring1 pwsout event enable. 0: disable ring1 pwsout event. 1: enable ring1 pwsout event, when ring1 falling edge detect erp control register 1 ? index e1h bit name r/w reset default description 7-6 reserved - - - reserved 5 s3_ erp_ctrl1#_dis r/w vbat 0 if clear to ?0? erp_ctrl1# will output low when s3 state. else if set to ?1? erp_ctrl1# will output high when s3 state. 4 s3 _ erp_ctrl0#_dis r/w vbat 0 if clear to ?0? erp_ctrl0# will output low when s3 state. else if set to ?1? erp_ctrl0# will output high when s3 state. 3 s5 _ erp_ctrl1#_dis r/w vbat 1 if clear to ?0? erp_ctrl1# will output low when s5 state. else if set to ?1? erp_ctrl1# will output high when s5 state. 2 s5 _ erp_ctrl0#_dis r/w vbat 1 if clear to ?0? erp_ctrl0# will output low when s5 state. else if set to ?1? erp_ctrl0# will output high when s5 state. 1 ac_ erp_ctrl1#_dis r/w vbat 0 if clear to ?0? erp_ctrl1# will output low when after ac lost. else if set to ?1? erp_ctrl1# will output high when after ac lost. 0 ac_ erp_ctrl0#_dis r/w vbat 0 if clear to ?0? erp_ctrl0# will output low when after ac lost. else if set to ?1? erp_ctrl0# will output high when after ac lost. erp control register 2 ? index e2h bit name r/w reset default description 7 ac_lost r 5vsb 1 this bit is ac lost status and writes 1 to this bit will clear it. 6 reserved r/w vbat 0 reserved
F81867 dec, 2011 v0.12p 185 5 vsb_ctrl_en[1] r/w vbat 1?b0 0: disable erp_ctrl1# assert rsmrst low 1: enable erp_ctrl1# assert rsmrst low 4 vsb_ctrl_en[0] r/w vbat 1?b0 0: disable erp_ctrl0# assert rsmrst low 1: enable erp_ctrl0# assert rsmrst low 3-2 reserved r/w vbat 0 reserved 1 rsmrst_det_5v_n r/w vbat 0 device detects 5vsb power ok (4.4v) and vsb3v_in become high, and after ~50ms de-bounce time rsmrst will become high. but when user set this bit to 1. rsmrst will not check 5vsb power ok. 0 reserved r - - reserved erp pwsin de-bounce register ? index e3h bit name r/w reset default description 7-0 pwsin_deb_time r/w vbat 13h pwsin# pin input de-bounce time. the unit is 1ms, default is 20ms. erp rsmrst de-bounce register ? index e4h bit name r/w reset default description 7-0 rsmrst_deb_time r/w vbat 9h rsmrst internal de-bounce time. the unit is 1ms and default is 10ms. erp pwsout pulse width register ? index e5h bit name r/w reset default description 7-0 pwsout_pw r/w vbat c7h pwsout output pulse width. the unit is 1ms and default is 200ms. erp pwsin de-bounce register ? index e6h bit name r/w reset default description 7-0 pson_deb_time r/w vbat 13h pson# pin input de-bounce time. the unit is 1ms, default is 10ms. erp deep s5 delay register ? index e7h bit name r/w reset default description 7-0 ds5_delay_time r/w vbat 63h the delay time from s5 state to deep s5 state. the unit is 64ms and default is 6.4 sec. erp wakeup enable register ? index e8h bit name r/w reset default description 7 ri2_wakeup_en r/w vbat 0 set this bit to enable ri2# event to wakeup system. 6 reserved - - - reserved 5 ri1_wakeup_en r/w vbat 0 set this bit to enable ri1# event to wakeup system. 4 reserved r/w vbat 0 reserved 3 gp_wakeup_en r/w vbat 0 set this bit to enable gpio event to wakeup system. 2 tmout_wakeup_en r/w vbat 0 set this bit to enable timeout event to wakeup system. 1 mo_wakeup_en r/w vbat 0 set this bit to enable mouse event to wakeup system. 0 kb_wakeup_en r/w vbat 0 set this bit to enable keyboard event to wakeup system.
F81867 dec, 2011 v0.12p 186 erp deep s3 delay register ? index e9h bit name r/w reset default description 7-0 ds3_delay_time r/w vbat fh the delay time from s3 state to deep s3 state. the unit is 64ms and default is 1.024 sec. erp mode select register ? index ech bit name r/w reset default description 7-6 erp_mode r/w vbat 0 00: fintek g3? mode. 01: intel dsw + fintek g3` mode. 10: reserved. 11: intel dsw mode. 5 dpwrok_ctrl_en r/w vbat 0 set ?1? to enable dpwrok reset by erp_ctrl1#. 4 soft_start_en r/w vbat 1 0: disable erp soft start. 1: enable erp soft start. 3-2 soft_start_rate r/w vbat 1h the soft start rate. 00: 5ms. 01: 10ms. 10: 27ms. 11: 54ms. 1-0 reserved - - - reserved erp wdt control register ? index edh bit name r/w reset default description 7-6 erp_wd_time[11:10] r/w vbat - time of erp watchdog timer. write index eeh will load watchdog time. 7-5 reserved r - - reserved 4 erp_wdtmout_status r vbat - watchdog timeout status. 3-2 erp_wd_time[9:8] r/w vbat - reserved 1 wd_unit r/w vbat 0 erp wdt unit. it is the time unit of erp_wd_time. 0: 1sec. 1: 60 sec. 0 wd_en r/w vbat 0 set ?1? to enable erp wdt. au to clear if timeout occurred. erp wdt time register ? index eeh bit name r/w reset default description 7-0 erp_wd_time r/w vbat 0 time of erp watchdog timer.
F81867 dec, 2011 v0.12p 187 7.11 rtc ram registers (ldn 0x0b) register 0x[hex] register name default value msb lsb 30 rtc ram enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 0 1 61 base address low register 1 0 0 1 0 1 0 1 rtc ram enable register ? index 30h bit name r/w reset default description 7-1 reserved - - - reserved 0 rtc_ram_en r/w vbat 1 0: disable rtc ram. 1: enable rtc ram. base address high register ? index 60h bit name r/w reset default description 7-0 base_addr_hi r/w vbat 02h the msb of rtc ram base address. base address low register ? index 61h bit name r/w reset default description 7-0 base_addr_lo r/w vbat 95h the lsb of rtc ram base address. the rtc ram is accessed by index/data port. the index port is {base_addr_hi, base_addr _lo[7:1],1?b0} and the data port is {base_addr_hi, base_addr_l o[7:1], 1?b1}. write the index first to select the ram address and then read/wr ite data port to access the context of ram. 7.12 h2e configurati on registers (ldn 0x0e) register 0x[hex] register name default value msb lsb 30 h2e i/o enable register - - - - - - - 0 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 0 0 0 0 0 0 0 70 h2e irq channel select register - - - - 0 0 0 0 fdc device enable register ? index 30h bit name r/w reset default description 7-1 reserved - - - reserved 0 h2e_en r/w 5vsb 1 0: disable h2e. 1: enable h2e.
F81867 dec, 2011 v0.12p 188 base address high register ? index 60h bit name r/w reset default description 7-0 base_addr_hi r/w 5vsb 00h the msb of h2e base address. base address low register ? index 61h bit name r/w reset default description 7-0 base_addr_lo r/w 5vsb 00h the lsb of h2e base address. irq channel select register ? index 70h bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 selh2eirq r/w 5vsb 00h select the irq channel for h2e. 7.13 debug port host side registers (ldn 0x0f ) register 0x[hex] register name default value msb lsb 30 debug port i/o port enable register - - - - - - - 0 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 0 0 0 0 0 0 0 debug port i/o port enable register ? index 30h bit name r/w reset default description 7-1 reserved - - - reserved 0 dbport_io_en r/w 5vsb 0 0: disable debug port i/o port. 1: enable debug port i/o port. base address high register ? index 60h bit name r/w reset default description 7-0 base_addr_hi r/w 5vsb 00h the msb of debug port base address. base address low register ? index 61h bit name r/w reset default description 7-0 base_addr_lo r/w 5vsb 00h the lsb of debug port base address. debug port read data register ? offset + 0x00 bit name r/w reset default description 7-0 dbport_data r 5vsb 00h the reading of c side register from the debug port. debug port control register ? offset + 0x01 bit name r/w reset default description 7 brk_prt_trig r - 0 status of breakpoint trigger.
F81867 dec, 2011 v0.12p 189 6-1 reserved - 5vsb - reserved 0 dbport_en r/w 5vsb 0 set ?!? to enable debug port. debug port register could be accessed by set address to 0x3200 + offset. to access the c side register including sfr and ram data. entry key should be entered via the debug port c side register. debug port control register ? offset + 0x01 bit name r/w reset default description 7 brk_prt_trig r 5vsb 0 status of breakpoint trigger. 6-1 reserved - - - reserved 0 dbport_en r/w 5vsb 0 set ?!? to enable debug port. debug port register could be accessed by set address to 0x3200 + offset. to access the c side register including sfr and ram data. entry key should be entered via debug port c side register. debug port address low byte register ? offset + 0x04 bit name r/w reset default description 7-0 dbport_l_addr r/w 5vsb 0 address low byte for c side register address. debug port address high byte register ? offset + 0x05 bit name r/w reset default description 7-0 dbport_h_addr r/w 5vsb 0 address high byte for c side register address. 7.14 uart1 registers (cr10) ?-? reserved or tri-state register 0x[hex] register name default value msb lsb 30 device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 1 61 base address low register 1 1 1 1 1 0 0 0 70 irq channel select register - - - - 0 1 0 0 f0 irq share register 0 0 0 0 - - 0 0 f2 clock select register - - - - - - 0 0 f4 9bit-mode slave address register 0 0 0 0 0 0 0 0 f5 9bit-mode slave address mask register 0 0 0 0 0 0 0 0 f6 fifo mode register 0 0 0 0 0 - 0 0 uart 1 device enable register ? index 30h bit name r/w reset default description 7-1 reserved - - - reserved 0 uart 1_en r/w lreset# 1 0: disable uart 1 i/o port. 1: enable uart 1 i/o port.
F81867 dec, 2011 v0.12p 190 base address high register ? index 60h bit name r/w reset default description 7-0 base_addr_hi r/w lreset# 03h the msb of uart 1 base address. base address low register ? index 61h bit name r/w reset default description 7-0 base_addr_lo r/w lreset# f8h the lsb of uart 1 base address. irq channel select register ? index 70h bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 selur1irq r/w lreset# 4h select the irq channel for uart 1. irq share register ? index f0h bit name r/w reset default description 7 9bit_mode r/w lreset# 0 0: normal uart function 1: enable 9-bit mode (multi-drop mode). in the 9-bit mode, the parity bit becomes the address/data bit. 6 auto_addr r/w lreset# 0 this bit works only in 9-bit mode. 0: the sm2 bit will be cleared by host, so that data could be received. 1: the sm2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by saddr and saden) 5 rs485_inv r/w lrest# 0 invert rts# if rs485_en is set. 4 rs485_en r/w lreset# 0 0: rs232 driver. 1: rs485 driver. rts# is driven high automatically when transmitting data, otherwise is kept low . 3-2 reserved - - - reserved. 1 irq_mode0 r/w lreset# 0 irq_mode1 and irq_mode0 will select the uart1 interrupt mode if irq sharing is enabled. 00 : sharing irq active low level mode. 01 : sharing irq active high edge mode. 10 : sharing irq active high level mode. 11 : reserved. this bit is effective at ir q is sharing with the other device (irq_share, bit 1). 0 irq_share r/w lreset# 0 0 : irq is not sharing with the other device. 1 : irq is sharing with the other device. clock register ? index f2h bit name r/w reset default description 7-2 reserved - - - reserved. 1-0 uart1_clk_sel r/w lreset# 0 select the clock source for uart1. 00: 1.8432mhz. 01: 18.432mhz. 10: 24mhz. 11: 14.769mhz.
F81867 dec, 2011 v0.12p 191 9bit-mode slave address register ? index f4h bit name r/w reset default description 7-0 saddr r/w lreset# 00h this byte accompanying with saden will determine the given address and broadcast address in 9-bit mode. the uart will response to both given and broadcast address. following description determines the given address and broadcast address: 1. given address: if bit n of saden is ?0?, then the corresponding bit of saddr is don?t care. 2. broadcast address: if bit n of ored saddr and saden is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr 0101_1100b saden 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b 9bit-mode slave address mask register ? index f5h bit name r/w reset default description 7-0 saden r/w lreset# 00h this byte accompanying with saddr will determine the given address and broadcast address in 9-bit mode. the uart will response to both given and broadcast address. following description determines the given address and broadcast address: 3. given address: if bit n of saden is ?0?, then the corresponding bit of saddr is don?t care. 4. broadcast address: if bit n of ored saddr and saden is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr 0101_1100b saden 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b fifo select register ? index f6h bit name r/w reset default description 7 tx_del_1bit r/w lrest# 0 0: tx will start transmit immediately after writing thr. 1: tx will delay 1 bit time to transmit after writing thr. 6 tx_int_mode r/w lreset# 0 0: tx will assert interrupt when thr is empty. 1: tx will assert interrupt when thr and shift register is empty. 5-4 rxfthr_mode r/w lreset# 0 the rx fifo threshold select. 00: fifo threshold is set by rxfthr. 01: fifo threshold will be 2x of rxfthr. 10: fifo threshold will be 4x of rxfthr. 11: fifo threshold will be 8x of rxfthr. 3 irq_mode1 r/w lrest# 0 irq_mode1 and irq_mode0 will select the uart1 interrupt mode if irq sharing is enabled. 00 : sharing irq active low level mode. 01 : sharing irq active high edge mode. 10 : sharing irq active high level mode. 11 : reserved. this bit is effective at irq is sharing with the other device (irq_share, bit 1).
F81867 dec, 2011 v0.12p 192 2 reserved - - - reserved. 1-0 fifo_mode r/w lreset# 00h select the fifo depth. 00: 16-byte fifo. 01: 32-byte fifo. 10: 64-byte fifo. 11: 128-byte fifo. 7.15 uart2 registers (cr11) ?-? reserved or tri-state register 0x[hex] register name default value msb lsb 30 device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 0 61 base address low register 1 1 1 1 1 0 0 0 f0 irq share register - - - - 0 0 1 1 f2 clock select register 0 0 0 0 - - 0 0 f4 9bit-mode slave address register - - - - - - 0 0 f5 9bit-mode slave address mask register 0 0 0 0 0 0 0 0 f0 irq share register 0 0 0 0 0 0 0 0 f6 fifo mode register 0 0 0 0 0 - 0 0 uart 2 device enable register ? index 30h bit name r/w reset default description 7-1 reserved - - - reserved 0 uart2_en r/w lreset# 1 0: disable uart 2 i/o port. 1: enable uart 2 i/o port. base address high register ? index 60h bit name r/w reset default description 7-0 base_addr_hi r/w lreset# 02h the msb of uart 2 base address. base address low register ? index 61h bit name r/w reset default description 7-1 base_addr_lo r/w lreset# f8h the lsb of uart 2 base address. irq channel select register ? index 70h bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 selur12rq r/w lreset# 3h select the irq channel for uart 2.
F81867 dec, 2011 v0.12p 193 irq share register ? index f0h bit name r/w reset default description 7 9bit_mode r/w lreset# 0 0: normal uart function 1: enable 9-bit mode (multi-drop mode). in the 9-bit mode, the parity bit becomes the address/data bit. 6 auto_addr r/w lreset# 0 this bit works only in 9-bit mode. 0: the sm2 bit will be cleared by host, so that data could be received. 1: the sm2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by saddr and saden) 5 rs485_inv r/w lreset# 0 invert rts# if rs485_en is set. 4 rs485_en r/w lreset# 0 0: rs232 driver. 1: rs485 driver. rts# is driven high automatically when transmitting data, otherwise is kept low . 3-2 reserved - - - reserved. 1 irq_mode0 r/w lreset# 0 irq_mode1 and irq_mode0 will select the uart2 interrupt mode if irq sharing is enabled. 00 : sharing irq active low level mode. 01 : sharing irq active high edge mode. 10 : sharing irq active high level mode. 11 : reserved. this bit is effective at ir q is sharing with the other device (irq_share, bit 1). 0 irq_share r/w lreset# 0 0 : irq is not sharing with the other device. 1 : irq is sharing with the other device. clock register ? index f2h bit name r/w reset default description 7-2 reserved - - - reserved. 1-0 uart2_clk_sel r/w lreset# 00b select the clock source for uart2. 00: 1.8432mhz. 01: 18.432mhz. 10: 24mhz. 11: 14.769mhz. 9bit-mode slave address register ? index f4h bit name r/w reset default description 7-0 saddr r/w lreset# 00h this byte accompanying with saden will determine the given address and broadcast address in 9-bit mode. the uart will response to both given and broadcast address. following description determines the given address and broadcast address: 5. given address: if bit n of saden is ?0?, then the corresponding bit of saddr is don?t care. 6. broadcast address: if bit n of ored saddr and saden is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr 0101_1100b saden 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b
F81867 dec, 2011 v0.12p 194 9bit-mode slave address mask register ? index f5h bit name r/w reset default description 7:0 saden r/w lreset# 00h this byte accompanying with saddr will determine the given address and broadcast address in 9-bit mode. the uart will response to both given and broadcast address. following description determines the given address and broadcast address: 7. given address: if bit n of saden is ?0?, then the corresponding bit of saddr is don?t care. 8. broadcast address: if bit n of ored saddr and saden is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr 0101_1100b saden 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b fifo select register ? index f6h bit name r/w reset default description 7 tx_del_1bit r/w lreset# 0 0: tx will start transmit immediately after writing thr. 1: tx will delay 1 bit time to transmit after writing thr. 6 tx_int_mode r/w lreset# 0 0: tx will assert interrupt when thr is empty. 1: tx will assert interrupt when thr and shift register is empty. 5-4 rxfthr_mode r/w lreset# 0 the rx fifo threshold select. 00: fifo threshold is set by rxfthr. 01: fifo threshold will be 2x of rxfthr. 10: fifo threshold will be 4x of rxfthr. 11: fifo threshold will be 8x of rxfthr. 3 irq_mode1 r/w lreset# 0 irq_mode1 and irq_mode0 will select the uart2 interrupt mode if irq sharing is enabled. 00 : sharing irq active low level mode. 01 : sharing irq active high edge mode. 10 : sharing irq active high level mode. 11 : reserved. this bit is effective at irq is sharing with the other device (irq_share, bit 1). 2 reserved - lreset# - reserved. 1-0 fifo_mode r/w lrest# 00h select the fifo depth. 00: 16-byte fifo. 01: 32-byte fifo. 10: 64-byte fifo. 11: 128-byte fifo.
F81867 dec, 2011 v0.12p 195 7.16 uart3 registers (cr12) ?-? reserved or tri-state register 0x[hex] register name default value msb lsb 30 device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 1 61 base address low register 1 1 1 0 1 0 0 0 f0 irq share register - - - - 0 0 1 1 f2 clock select register 0 0 0 0 - - 0 0 f4 9bit-mode slave address register - - - - - - 0 0 f5 9bit-mode slave address mask register 0 0 0 0 0 0 0 0 f0 irq share register 0 0 0 0 0 0 0 0 f6 fifo mode register 0 0 0 0 0 - 0 0 uart 3 device enable register ? index 30h bit name r/w reset default description 7-1 reserved - - - reserved 0 uart3_en r/w lreset# 1 0: disable uart 3 i/o port. 1: enable uart 3 i/o port. base address high register ? index 60h bit name r/w reset default description 7-0 base_addr_hi r/w lreset# 03h the msb of uart 3 base address. base address low register ? index 61h bit name r/w reset default description 7-0 base_addr_lo r/w lreset# e8h the lsb of uart 3 base address. irq channel select register ? index 70h bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 seluart3irq r/w lreset# 3h select the irq channel for uart 3. irq share register ? index f0h bit name r/w reset default description 7 9bit_mode r/w lreset# 0 0: normal uart function 1: enable 9-bit mode (multi-drop mode). in the 9-bit mode, the parity bit becomes the address/data bit. 6 auto_addr r/w lreset# 0 this bit works only in 9-bit mode. 0: the sm2 bit will be cleared by host, so that data could be received. 1: the sm2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by saddr and saden)
F81867 dec, 2011 v0.12p 196 5 rs485_inv r/w lreset# 0 invert rts# if rs485_en is set. 4 rs485_en r/w lreset# 0 0: rs232 driver. 1: rs485 driver. rts# is driven high automatically when transmitting data, otherwise is kept low . 3-2 reserved - - - reserved. 1 irq_mode0 r/w lreset# 0 irq_mode1 and irq_mode0 will select the uart3 interrupt mode if irq sharing is enabled. 00 : sharing irq active low level mode. 01 : sharing irq active high edge mode. 10 : sharing irq active high level mode. 11 : reserved. this bit is effective at ir q is sharing with the other device (irq_share, bit 1). 0 irq_share r/w lreset# 0 0 : irq is not sharing with other device. 1 : irq is sharing with other device. clock register ? index f2h bit name r/w reset default description 7-2 reserved - - - reserved. 1-0 uart3_clk_sel r/w lreset# 00b select the clock source for uart3. 00: 1.8432mhz. 01: 18.432mhz. 10: 24mhz. 11: 14.769mhz. 9bit-mode slave address register ? index f4h bit name r/w reset default description 7-0 saddr r/w lreset# 00h this byte accompanying with saden will determine the given address and broadcast address in 9-bit mode. the uart will response to both given and broadcast address. following description determines the given address and broadcast address: 9. given address: if bit n of saden is ?0?, then the corresponding bit of saddr is don?t care. 10. broadcast address: if bit n of ored saddr and saden is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr 0101_1100b saden 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b
F81867 dec, 2011 v0.12p 197 9bit-mode slave address mask register ? index f5h bit name r/w reset default description 7:0 saden r/w lreset# 00h this byte accompanying with saddr will determine the given address and broadcast address in 9-bit mode. the uart will response to both given and broadcast address. following description determines the given address and broadcast address: 11. given address: if bit n of saden is ?0?, then the corresponding bit of saddr is don?t care. 12. broadcast address: if bit n of ored saddr and saden is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr 0101_1100b saden 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b fifo select register ? index f6h bit name r/w reset default description 7 tx_del_1bit r/w lreset# 0 0: tx will start transmit immediately after writing thr. 1: tx will delay 1 bit time to transmit after writing thr. 6 tx_int_mode r/w lreset# 0 0: tx will assert interrupt when thr is empty. 1: tx will assert interrupt when thr and shift register is empty. 5-4 rxfthr_mode r/w lreset# 0 the rx fifo threshold select. 00: fifo threshold is set by rxfthr. 01: fifo threshold will be 2x of rxfthr. 10: fifo threshold will be 4x of rxfthr. 11: fifo threshold will be 8x of rxfthr. 3 irq_mode1 r/w lreset# 0 irq_mode1 and irq_mode0 will select the uart3 interrupt mode if irq sharing is enabled. 00 : sharing irq active low level mode. 01 : sharing irq active high edge mode. 10 : sharing irq active high level mode. 11 : reserved. this bit is effective at irq is sharing with the other device (irq_share, bit 1). 2 reserved - - - reserved. 1-0 fifo_mode r/w lreset# 00h select the fifo depth. 00: 16-byte fifo. 01: 32-byte fifo. 10: 64-byte fifo. 11: 128-byte fifo.
F81867 dec, 2011 v0.12p 198 7.17 uart4 registers (cr13) ?-? reserved or tri-state register 0x[hex] register name default value msb lsb 30 device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 0 61 base address low register 1 1 1 0 1 0 0 0 70 irq channel select register - - - - 0 0 1 1 f0 irq share register 0 0 0 0 - - 0 0 f2 clock select register - - - - - - 0 0 f4 9bit-mode slave address register 0 0 0 0 0 0 0 0 f5 9bit-mode slave address mask register 0 0 0 0 0 0 0 0 f6 fifo mode register 0 0 0 0 0 - 0 0 uart 4 device enable register ? index 30h bit name r/w reset default description 7-1 reserved - - - reserved 0 uart4_en r/w lreset# 1 0: disable uart 4 i/o port. 1: enable uart 4 i/o port. base address high register ? index 60h bit name r/w reset default description 7-0 base_addr_hi r/w lreset# 03h the msb of uart 4 base address. base address low register ? index 61h bit name r/w reset default description 7-0 base_addr_lo r/w lreset# e8h the lsb of uart 4 base address. irq channel select register ? index 70h bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 seluart4irq r/w lreset# 3h select the irq channel for uart 4. irq share register ? index f0h bit name r/w reset default description 7 9bit_mode r/w lreset# 0 0: normal uart function 1: enable 9-bit mode (multi-drop mode). in the 9-bit mode, the parity bit becomes the address/data bit. 6 auto_addr r/w lreset# 0 this bit works only in 9-bit mode. 0: the sm2 bit will be cleared by host, so that data could be received. 1: the sm2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by saddr and saden)
F81867 dec, 2011 v0.12p 199 5 rs485_inv r/w lreset# 0 invert rts# if rs485_en is set. 4 rs485_en r/w lreset# 0 0: rs232 driver. 1: rs485 driver. rts# is driven high automatically when transmitting data, otherwise is kept low . 3-2 reserved - lreset# - reserved. 1 irq_mode0 r/w lreset# 0 irq_mode1 and irq_mode0 will select the uart4 interrupt mode if irq sharing is enabled. 00 : sharing irq active low level mode. 01 : sharing irq active high edge mode. 10 : sharing irq active high level mode. 11 : reserved. this bit is effective at ir q is sharing with the other device (irq_share, bit 1). 0 irq_share r/w lreset# 0 0 : irq is not sharing with other device. 1 : irq is sharing with other device. clock register ? index f2h bit name r/w reset default description 7-2 reserved - - - reserved. 1-0 uart4_clk_sel r/w lreset# 00b select the clock source for uart4. 00: 1.8432mhz. 01: 18.432mhz. 10: 24mhz. 11: 14.769mhz. 9bit-mode slave address register ? index f4h bit name r/w reset default description 7-0 saddr r/w lreset# 00h this byte accompanying with saden will determine the given address and broadcast address in 9-bit mode. the uart will response to both given and broadcast address. following description determines the given address and broadcast address: 13. given address: if bit n of saden is ?0?, then the corresponding bit of saddr is don?t care. 14. broadcast address: if bit n of ored saddr and saden is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr 0101_1100b saden 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b
F81867 dec, 2011 v0.12p 200 9bit-mode slave address mask register ? index f5h bit name r/w reset default description 7:0 saden r/w lreset# 00h this byte accompanying with saddr will determine the given address and broadcast address in 9-bit mode. the uart will response to both given and broadcast address. following description determines the given address and broadcast address: 15. given address: if bit n of saden is ?0?, then the corresponding bit of saddr is don?t care. 16. broadcast address: if bit n of ored saddr and saden is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr 0101_1100b saden 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b fifo select register ? index f6h bit name r/w reset default description 7 tx_del_1bit r/w lreset# 0 0: tx will start transmit immediately after writing thr. 1: tx will delay 1 bit time to transmit after writing thr. 6 tx_int_mode r/w lreset# 0 0: tx will assert interrupt when thr is empty. 1: tx will assert interrupt when thr and shift register is empty. 5-4 rxfthr_mode r/w lreset# 0 the rx fifo threshold select. 00: fifo threshold is set by rxfthr. 01: fifo threshold will be 2x of rxfthr. 10: fifo threshold will be 4x of rxfthr. 11: fifo threshold will be 8x of rxfthr. 3 irq_mode1 r/w lreset# 0 irq_mode1 and irq_mode0 will select the uart4 interrupt mode if irq sharing is enabled. 00 : sharing irq active low level mode. 01 : sharing irq active high edge mode. 10 : sharing irq active high level mode. 11 : reserved. this bit is effective at irq is sharing with the other device (irq_share, bit 1). 2 reserved - - - reserved. 1-0 fifo_mode r/w lreset# 00h select the fifo depth. 00: 16-byte fifo. 01: 32-byte fifo. 10: 64-byte fifo. 11: 128-byte fifo.
F81867 dec, 2011 v0.12p 201 7.18 uart5 registers (cr14) ?-? reserved or tri-state register 0x[hex] register name default value msb lsb 30 device enable register - - - - - - - 0 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 0 0 0 0 0 0 0 70 irq channel select register - - - - 0 0 1 1 f0 irq share register 0 0 0 0 - - 0 0 f2 clock select register 0 0 0 0 - - 0 0 f4 9bit-mode slave address register - - - - - - 0 0 f5 9bit-mode slave address mask register 0 0 0 0 0 0 0 0 f0 irq share register 0 0 0 0 0 0 0 0 f6 fifo mode register 0 0 0 0 0 - 0 0 uart 5 device enable register ? index 30h bit name r/w reset default description 7-1 reserved - - - reserved 0 uart5_en r/w lreset# 0 0: disable uart 5 i/o port. 1: enable uart 5 i/o port. base address high register ? index 60h bit name r/w reset default description 7-0 base_addr_hi r/w lreset# 00h the msb of uart 5 base address. base address low register ? index 61h bit name r/w reset default description 7-0 base_addr_lo r/w lreset# 00h the lsb of uart 5 base address. irq channel select register ? index 70h bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 seluart5irq r/w lreset# 3h select the irq channel for uart 5. irq share register ? index f0h bit name r/w reset default description 7 9bit_mode r/w lreset# 0 0: normal uart function 1: enable 9-bit mode (multi-drop mode). in the 9-bit mode, the parity bit becomes the address/data bit.
F81867 dec, 2011 v0.12p 202 6 auto_addr r/w lreset# 0 this bit works only in 9-bit mode. 0: the sm2 bit will be cleared by host, so that data could be received. 1: the sm2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by saddr and saden) 5 rs485_inv r/w lreset# 0 invert rts# if rs485_en is set. 4 rs485_en r/w lreset# 0 0: rs232 driver. 1: rs485 driver. rts# is driven high automatically when transmitting data, otherwise is kept low . 3-2 reserved - lreset# - reserved. 1 irq_mode0 r/w lreset# 0 irq_mode1 and irq_mode0 will select the uart5 interrupt mode if irq sharing is enabled. 00 : sharing irq active low level mode. 01 : sharing irq active high edge mode. 10 : sharing irq active high level mode. 11 : reserved. this bit is effective at ir q is sharing with the other device (irq_share, bit 1). 0 irq_share r/w lreset# 0 0 : irq is not sharing with other device. 1 : irq is sharing with other device. clock register ? index f2h bit name r/w reset default description 7-2 reserved - - - reserved. 1-0 uart5_clk_sel r/w lreset# 00b select the clock source for uart5. 00: 1.8432mhz. 01: 18.432mhz. 10: 24mhz. 11: 14.769mhz. 9bit-mode slave address register ? index f4h bit name r/w reset default description 7-0 saddr r/w lreset# 00h this byte accompanying with saden will determine the given address and broadcast address in 9-bit mode. the uart will response to both given and broadcast address. following description determines the given address and broadcast address: 17. given address: if bit n of saden is ?0?, then the corresponding bit of saddr is don?t care. 18. broadcast address: if bit n of ored saddr and saden is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr 0101_1100b saden 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b
F81867 dec, 2011 v0.12p 203 9bit-mode slave address mask register ? index f5h bit name r/w reset default description 7:0 saden r/w lreset# 00h this byte accompanying with saddr will determine the given address and broadcast address in 9-bit mode. the uart will response to both given and broadcast address. following description determines the given address and broadcast address: 19. given address: if bit n of saden is ?0?, then the corresponding bit of saddr is don?t care. 20. broadcast address: if bit n of ored saddr and saden is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr 0101_1100b saden 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b fifo select register ? index f6h bit name r/w reset default description 7 tx_del_1bit r/w lreset# 0 0: tx will start transmit immediately after writing thr. 1: tx will delay 1 bit time to transmit after writing thr. 6 tx_int_mode r/w lreset# 0 0: tx will assert interrupt when thr is empty. 1: tx will assert interrupt when thr and shift register is empty. 5-4 rxfthr_mode r/w lreset# 0 the rx fifo threshold select. 00: fifo threshold is set by rxfthr. 01: fifo threshold will be 2x of rxfthr. 10: fifo threshold will be 4x of rxfthr. 11: fifo threshold will be 8x of rxfthr. 3 irq_mode1 r/w lreset# 0 irq_mode1 and irq_mode0 will select the uart5 interrupt mode if irq sharing is enabled. 00 : sharing irq active low level mode. 01 : sharing irq active high edge mode. 10 : sharing irq active high level mode. 11 : reserved. this bit is effective at irq is sharing with the other device (irq_share, bit 1). 2 reserved - - - reserved. 1-0 fifo_mode r/w lreset# 00h select the fifo depth. 00: 16-byte fifo. 01: 32-byte fifo. 10: 64-byte fifo. 11: 128-byte fifo.
F81867 dec, 2011 v0.12p 204 7.19 uart6 registers (cr15) ?-? reserved or tri-state register 0x[hex] register name default value msb lsb 30 device enable register - - - - - - - 0 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 0 0 0 0 0 0 0 70 irq channel select register - - - - 0 0 1 1 f0 irq share register 0 0 0 0 0 0 0 0 f1 ir mode register - - - 0 0 1 0 0 f2 clock select register - - - 0 0 0 0 0 f4 9bit-mode slave address register - - - - - - 0 0 f5 9bit-mode slave address mask register 0 0 0 0 0 0 0 0 f0 irq share register 0 0 0 0 0 0 0 0 f6 fifo mode register 0 0 0 0 0 - 0 0 uart 6 device enable register ? index 30h bit name r/w reset default description 7-1 reserved - - - reserved 0 uart6_en r/w lreset# 0 0: disable uart 6 i/o port. 1: enable uart 6 i/o port. base address high register ? index 60h bit name r/w reset default description 7-0 base_addr_hi r/w lreset# 00h the msb of uart 6 base address. base address low register ? index 61h bit name r/w reset default description 7-0 base_addr_lo r/w lreset# 00h the lsb of uart 6 base address. irq channel select register ? index 70h bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 seluart6irq r/w lreset# 3h select the irq channel for uart 6. irq share register ? index f0h bit name r/w reset default description 7 9bit_mode r/w lreset# 0 0: normal uart function 1: enable 9-bit mode (multi-drop mode). in the 9-bit mode, the parity bit becomes the address/data bit.
F81867 dec, 2011 v0.12p 205 6 auto_addr r/w lreset# 0 this bit works only in 9-bit mode. 0: the sm2 bit will be cleared by host, so that data could be received. 1: the sm2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by saddr and saden) 5 rs485_inv r/w lreset# 0 invert rts# if rs485_en is set. 4 rs485_en r/w lreset# 0 0: rs232 driver. 1: rs485 driver. rts# is driven high automatically when transmitting data, otherwise is kept low . 3 rxw4c_ir r/w lreset# 0 0 : no reception delay when sir is changed from tx to rx. 1 : reception delay 4 character-time when sir is changed from tx to rx. 2 txw4c_ir r/w lreset# 0 0 : no transmission delay when sir is changed from rx to tx. 1 : transmission delay 4 character-time when sir is changed from rx to tx. 1 irq_mode0 r/w lreset# 0 irq_mode1 and irq_mode0 will select the uart5 interrupt mode if irq sharing is enabled. 00 : sharing irq active low level mode. 01 : sharing irq active high edge mode. 10 : sharing irq active high level mode. 11 : reserved. this bit is effective at ir q is sharing with the other device (irq_share, bit 1). 0 irq_share r/w lreset# 0 0 : irq is not sharing with other device. 1 : irq is sharing with other device. ir mode select register ? index f1h bit name r/w reset default description 7-5 reserved - - - reserved. return 010b when read. 4-3 irmode1 irmode0 r/w lreset# 00b 0x: disable ir1 function. 10 : enable ir1 function, active pulse is 1.6us. 11 : enable ir1 function, active pulse is 3/16 bit time. 2 hduplx r/w lreset# 1 0 : full duplex function for ir self test. 1 : half duplex function. return 1 when read. 1 txinv_ir r/w lreset# 0 0 : irtx is not inversed. 1 : inverse the irtx. 0 rxinv_ir r/w lreset# 0 0 : irrx is not inversed. 1 : inverse the irrx. clock register ? index f2h bit name r/w reset default description 7-2 reserved - - - reserved. 1-0 uart6_clk_sel r/w lreset# 00b select the clock source for uart6. 00: 1.8432mhz. 01: 18.432mhz. 10: 24mhz. 11: 14.769mhz.
F81867 dec, 2011 v0.12p 206 9bit-mode slave address register ? index f4h bit name r/w reset default description 7-0 saddr r/w lreset# 00h this byte accompanying with saden will determine the given address and broadcast address in 9-bit mode. the uart will response to both given and broadcast address. following description determines the given address and broadcast address: 21. given address: if bit n of saden is ?0?, then the corresponding bit of saddr is don?t care. 22. broadcast address: if bit n of ored saddr and saden is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr 0101_1100b saden 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b 9bit-mode slave address mask register ? index f5h bit name r/w reset default description 7:0 saden r/w lreset# 00h this byte accompanying with saddr will determine the given address and broadcast address in 9-bit mode. the uart will response to both given and broadcast address. following description determines the given address and broadcast address: 23. given address: if bit n of saden is ?0?, then the corresponding bit of saddr is don?t care. 24. broadcast address: if bit n of ored saddr and saden is ?0?, don?t care that bit. the remaining bit which is ?1? is compared to the received address. ex. saddr 0101_1100b saden 1111_1001b given address 0101_1xx0b broadcast address 1111_11x1b fifo select register ? index f6h bit name r/w reset default description 7 tx_del_1bit r/w lreset# 0 0: tx will start transmit immediately after writing thr. 1: tx will delay 1 bit time to transmit after writing thr. 6 tx_int_mode r/w lreset# 0 0: tx will assert interrupt when thr is empty. 1: tx will assert interrupt when thr and shift register is empty. 5-4 rxfthr_mode r/w lreset# 0 the rx fifo threshold select. 00: fifo threshold is set by rxfthr. 01: fifo threshold will be 2x of rxfthr. 10: fifo threshold will be 4x of rxfthr. 11: fifo threshold will be 8x of rxfthr.
F81867 dec, 2011 v0.12p 207 3 irq_mode1 r/w lreset# 0 irq_mode1 and irq_mode0 will select the uart5 interrupt mode if irq sharing is enabled. 00 : sharing irq active low level mode. 01 : sharing irq active high edge mode. 10 : sharing irq active high level mode. 11 : reserved. this bit is effective at irq is sharing with the other device (irq_share, bit 1). 2 reserved - - - reserved. 1-0 fifo_mode r/w lreset# 00h select the fifo depth. 00: 16-byte fifo. 01: 32-byte fifo. 10: 64-byte fifo. 11: 128-byte fifo. 7.20 c side registers the c side registers are bas ically accessed by c with the movx instruction. ev ery device (peripheral) has its own base address. the address mapping is list as following table. device base address range remark intc 0x1000 256 bytes interrupt control gctrl 0x1100 256 bytes general control pwm 0x1200 256 bytes sram1 0x1300 256 bytes sram2 0x1400 256 bytes e2h 0x1500 256 bytes ec to host embedded flash 0x1f00 256 bytes hwm 0x2000 256 bytes could accessed by host side gpio 0x2100 256 bytes could accessed by host side kbc 0x2200 256 bytes acpi 0x2300 256 bytes cfg 0x2400 256 bytes configuration; could be accessed by host side ram 0x2500 256 bytes could be accessed by host side cir 0x2600 256 bytes c_sfr 0x3000 256 bytes for debug port only c_ram 0x3100 256 bytes for debug port only dbport 0x3200 256 bytes for debug port only
F81867 dec, 2011 v0.12p 208 7.20.1 interrupt control c side register (base address 0x1000, 256 bytes) interrupt status register ? offset 01h bit name r/w reset default description 7 reserved - - - reserved. 6 cir_int_st r/wc 5vsb 0 0: no cir interrupt event. 1: a cir interrupt event occurs. write ?1? to clear this bit. 5 p80_int_st r/wc 5vsb 0 0: no 0x80 port interrupt event. 1: a 0x80 port interrupt event occu rs. write ?1? to clear this bit. 4 h2e_int_st r/wc 5vsb 0 0: no h2e interrupt event. 1: a h2e interrupt event occurs. write ?1? to clear this bit. 3 acpi_int_st r/wc 5vsb 0 0: no acpi interrupt event. 1: an acpi interrupt event occurs. write ?1? to clear this bit. 2 kbc_int_st r/wc 5vsb 0 0: no kbc interrupt event. 1: a kbc interrupt event occurs. write ?1? to clear this bit. 1 gpio_int_st r/wc 5vsb 0 0: no gpio interrupt event. 1: a gpio interrupt event occurs. write ?1? to clear this bit. 0 hm_int_st r/wc 5vsb 0 0: no hardware monitor interrupt event. 1: a hardware monitor interrupt event occurs. write ?1? to clear this bit. interrupt enable register ? offset 03h bit name r/w reset default description 7 reserved - - - reserved. 6 cir_int_en r/wc 5vsb 0 0: disable cir interrupt. 1: enable cir interrupt. 5 p80_int_en r/wc 5vsb 0 0: disable 0x80 port interrupt. 1: enable 0x80 port interrupt. 4 h2e_int_en r/wc 5vsb 0 0: disable host to ec interrupt. 1: enable host to ec interrupt. 3 acpi_int_en r/wc 5vsb 0 0: disable acpi interrupt. 1: enable acpi interrupt. 2 kbc_int_en r/wc 5vsb 0 0: disable kbc interrupt. 1: enable kbc interrupt. 1 gpio_int_en r/wc 5vsb 0 0: disable gpio interrupt. 1: enable gpio interrupt. 0 hm_int_en r/wc 5vsb 0 0: disable hm interrupt. 1: enable hm interrupt. the peripheral interrupt is asserted to int1# of c. interrupt polarity register ? offset 05h bit name r/w reset default description 7 reserved - - - reserved. 6 cir_int_pol r/wc 5vsb 0 0: rising edge of event will trigger an interrupt. 1: falling edge of event will trigger an interrupt.
F81867 dec, 2011 v0.12p 209 5 p80_int_pol r/wc 5vsb 0 0: rising edge of event will trigger an interrupt. 1: falling edge of event will trigger an interrupt. 4 h2e_int_pol r/wc 5vsb 0 0: rising edge of event will trigger an interrupt. 1: falling edge of event will trigger an interrupt. 3 acpi_int_pol r/wc 5vsb 0 0: rising edge of event will trigger an interrupt. 1: falling edge of event will trigger an interrupt. 2 kbc_int_pol r/wc 5vsb 0 0: rising edge of event will trigger an interrupt. 1: falling edge of event will trigger an interrupt. 1 gpio_int_pol r/wc 5vsb 0 0: rising edge of event will trigger an interrupt. 1: falling edge of event will trigger an interrupt. 0 hm_int_pol r/wc 5vsb 0 0: rising edge of event will trigger an interrupt. 1: falling edge of event will trigger an interrupt. interrupt status 3 register ? offset 10h bit name r/w reset default description 7-2 reserved - - - reserved. 1 pd_int_st r/wc 5vsb 0 0: no power down event 1: a power down event occurs. it is set by falling edge of pwrok. it is cleared by read this bit. 0 dbport_int_st r/wc 5vsb 0 0: no debug port event. 1: a debug port interrupt event occurs. clear by reading this bit. power fail register ? offset 11h bit name r/w reset default description 7-2 reserved - - - reserved. 1 pwrok r 5vsb 0 status of pwrok. 0 pd_int_en r/wc 5vsb 0 set ?1? to enable power fail interrupt. 7.20.2 general control c side register (base address 0x1100, 256 bytes) chip id 1 register ? offset 00h bit name r/w reset default description 7-0 chipid1 r - 0x00 chip id 1 chip id 2 register ? offset 01h bit name r/w reset default description 7-0 chipid2 r - 0x95 chip id 2 c reset select register ? offset 04h bit name r/w reset default description 7-1 reserved - - - reserved.
F81867 dec, 2011 v0.12p 210 0 ec_grst r/w 5vsb 0 0: c and peripherals are reset by 5vsb power on reset, c watchdog timerout reset and debug port exit reset. 1: c and peripherals are reset by 5vsb power on reset and debug port exit reset. wdt reset gate 1 register ? offset 05h bit name r/w reset default description 7 smfi_wd_rst_dis r/w 5vsb 1 0: smfi will reset by c watchdog timeout. 1: smfi won?t be reset by c watchdog timeout. 6-5 reserved - - - reserved. 4 intc_wd_rst_dis r/w 5vsb 1 0: intc will reset by c watchdog timeout. 1: intc won?t be reset by c watchdog timeout. 3-2 reserved - - - reserved. 1 cir_wd_rst_dis r/w 5vsb 1 0: cir will reset by c watchdog timeout. 1: cir won?t be reset by c watchdog timeout. 0 pwm_wd_rst_dis r/w 5vsb 1 0: pwm will reset by c watchdog timeout. 1: pwm won?t be reset by c watchdog timeout. wdt reset gate 2 register ? offset 06h bit name r/w reset default description 7-4 reserved - - - reserved. 3 acpi_wd_rst_dis r/w 5vsb 1 0: acpi will reset by c watchdog timeout. 1: acpi won?t be reset by c watchdog timeout. 2 kbc_wd_rst_dis r/w 5vsb 1 0: kbc will reset by c watchdog timeout. 1: kbc won?t be reset by c watchdog timeout. 1 gpio_wd_rst_dis r/w 5vsb 1 0: gpio will reset by c watchdog timeout. 1: gpio won?t be reset by c watchdog timeout. 0 cfg_wd_rst_dis r/w 5vsb 1 0: cfg will reset by c watchdog timeout. 1: cfg won?t be reset by c watchdog timeout rtc ram write protect register ? offset 06h bit name r/w reset default description 7 rtc_wr_dis_7 r/w 5vsb 0 set ?1? to enable write protect for rtc ram index 0xf0 ~ 0xff. 6 rtc_wr_dis_6 r/w 5vsb 0 set ?1? to enable write protect for rtc ram index 0xe0 ~ 0xef. 5 rtc_wr_dis_5 r/w 5vsb 0 set ?1? to enable write protect for rtc ram index 0xd0 ~ 0xdf.
F81867 dec, 2011 v0.12p 211 4 rtc_wr_dis_4 r/w 5vsb 0 set ?1? to enable write protect for rtc ram index 0xc0 ~ 0xcf. 3 rtc_wr_dis_3 r/w 5vsb 0 set ?1? to enable write protect for rtc ram index 0xb0 ~ 0xbf. 2 rtc_wr_dis_2 r/w 5vsb 0 set ?1? to enable write protect for rtc ram index 0xa0 ~ 0xaf. 1 rtc_wr_dis_1 r/w 5vsb 0 set ?1? to enable write protect for rtc ram index 0x90 ~ 0x9f. 0 rtc_wr_dis_0 r/w 5vsb 0 set ?1? to enable write protect for rtc ram index 0x80 ~ 0x8f. software reset 1 register ? offset 10h bit name r/w reset default description 7 rsmfi w - - write ?1? to assert a soft ware reset to spi block. 6-5 reserved - - - reserved. 4 rintc w - - write ?1? to assert a soft ware reset to intc block. 3-2 reserved - - - reserved. 1 rcir w - - write ?1? to assert a soft ware reset to cir block. 0 rpwm w - - write ?1? to assert a so ftware reset to pwm block. software reset 2 register ? offset 11h bit name r/w reset default description 7-4 reserved - - - reserved. 3 acpi_wd_rst_dis r/w 5vsb 1 0: acpi will reset by c watchdog timeout. 1: acpi won?t be reset by c watchdog timeout. 2 kbc_wd_rst_dis r/w 5vsb 1 0: kbc will reset by c watchdog timeout. 1: kbc won?t be reset by c watchdog timeout. 1 gpio_wd_rst_dis r/w 5vsb 1 0: gpio will reset by c watchdog timeout. 1: gpio won?t be reset by c watchdog timeout. 0 cfg_wd_rst_dis r/w 5vsb 1 0: cfg will reset by c watchdog timeout. 1: cfg won?t be reset by c watchdog timeout. software reset 2 register ? offset 11h bit name r/w reset default description 7-4 reserved - - - reserved. 3 racpi w 5vsb - write ?1? to assert a soft ware reset to acpi block. 2 rkbc w 5vsb - write ?1? to assert a soft ware reset to kbc block. 1 rgpio w 5vsb - write ?1? to assert a soft ware reset to gpio block. 0 rcfg w 5vsb - write ?1? to assert a soft ware reset to cfg block.
F81867 dec, 2011 v0.12p 212 7.20.3 pwm control c side register (base address 0x1200, 256 bytes) clock group 0 divisor register ? offset 00h bit name r/w reset default description 7-0 gr0_div r/w 5vsb 0x00 clock group 0 divisor. the group 0 clock will be 12mhz/(gr0_div +1)*256. clock group 1 divisor register ? offset 01h bit name r/w reset default description 7-0 gr1_div r/w 5vsb 0x00 clock group 1 divisor. the group 2 clock will be 12mhz/(gr0_div +1)*256. clock group 2 divisor register ? offset 02h bit name r/w reset default description 7-0 gr2_div r/w 5vsb 0x00 clock group 2 divisor. the group 2 clock will be 12mhz/(gr0_div +1)*256. clock group 3 divisor register ? offset 03h bit name r/w reset default description 7-0 gr3_div r/w 5vsb 0x00 clock group 3 divisor. the group 3 clock will be 12mhz/(gr0_div +1)*256. the pwm clock source could be sele ct among these four group clock. pwm polarity register ? offset 04h bit name r/w reset default description 7-4 reserved - - - reserved. 3 pwm3_pol r/w 5vsb 0 0: normal pwm output. 1: pwm output is inverted. 2 pwm2_pol r/w 5vsb 0 0: normal pwm output. 1: pwm output is inverted. 1 pwm1_pol r/w 5vsb 0 0: normal pwm output. 1: pwm output is inverted. 0 pwm0_pol r/w 5vsb 0 0: normal pwm output. 1: pwm output is inverted. pwm group select register ? offset 06h bit name r/w reset default description 7-6 pcs3 r/w 5vsb 00 00: pwm3 clock source is group 0 clock. 01: pwm3 clock source is group 1 clock. 10: pwm3 clock source is group 2 clock. 11: pwm3 clock source is group 3 clock. 5-4 pcs2 r/w 5vsb 00 00: pwm2 clock source is group 0 clock. 01: pwm2 clock source is group 1 clock. 10: pwm2 clock source is group 2 clock. 11: pwm2 clock source is group 3 clock.
F81867 dec, 2011 v0.12p 213 3-2 pcs1 r/w 5vsb 00 00: pwm1 clock source is group 0 clock. 01: pwm1 clock source is group 1 clock. 10: pwm1 clock source is group 2 clock. 11: pwm1 clock source is group 3 clock. 1-0 pcs0 r/w 5vsb 00 00: pwm0 clock source is group 0 clock. 01: pwm0 clock source is group 1 clock. 10: pwm0 clock source is group 2 clock. 11: pwm0 clock source is group 3 clock. pwm clock gate register ? offset 08h bit name r/w reset default description 7-4 reserved - - - reserved. 3 pcsgr3 r/w 5vsb 0 0: enable pwm3 clock. 1: disable pwm3 clock. 2 pcsgr2 r/w 5vsb 0 0: enable pwm2 clock. 1: disable pwm2 clock. 1 pcsgr1 r/w 5vsb 0 0: enable pwm1 clock. 1: disable pwm1 clock. 0 pcsgr0 r/w 5vsb 0 0: enable pwm0 clock. 1: disable pwm0 clock. pwm type register ? offset 09h bit name r/w reset default description 7-4 reserved - - - reserved. 3 pwm3_type r/w 5vsb 0 0: open drain. 1: push pull. 2 pwm2_type r/w 5vsb 0 0: open drain. 1: push pull. 1 pwm1_type r/w 5vsb 0 0: open drain. 1: push pull. 0 pwm0_type r/w 5vsb 0 0: open drain. 1: push pull. pwm enable register ? offset 0ah bit name r/w reset default description 7 soft_rst w 5vsb 0 write ?1? to software reset pwm block. 6-1 reserved - - - reserved. 0 pcce r/w 5vsb 0 0: disable pwm. all clocks will be disabled. 1: enable pwm. pwm0 duty control register ? offset 10h bit name r/w reset default description 7-0 dcr0 r/w 5vsb 0 the duty cycle of pwm0 will be (dcr0/255)*100%. set 0 to force stop and 0xff to force 100% duty.
F81867 dec, 2011 v0.12p 214 pwm1 duty control register ? offset 11h bit name r/w reset default description 7-0 dcr1 r/w 5vsb 0 the duty cycle of pwm1 will be (dcr1/255)*100%. set 0 to force stop and 0xff to force 100% duty. pwm2 duty control register ? offset 12h bit name r/w reset default description 7-0 dcr2 r/w 5vsb 0 the duty cycle of pwm2 will be (dcr2/255)*100%. set 0 to force stop and 0xff to force 100% duty. pwm3 duty control register ? offset 13h bit name r/w reset default description 7-0 dcr3 r/w 5vsb 0 the duty cycle of pwm3 will be (dcr3/255)*100%. set 0 to force stop and 0xff to force 100% duty. 7.20.4 c side sram1 register (base address 0x1300, 256 bytes) offset 00h ~ ffh, 256 bytes sram accssed by c, sram powered by i_vsb3v 7.20.5 c side sram2 register (base address 0x1400, 256 bytes) offset 00h ~ ffh, 256 bytes sram accssed by c, sram powered by i_vsb3v 7.20.6 host to ec control c side register (base address 0x1500, 256 bytes) host to ec control register ? offset 00h bit name r/w reset default description 7 p80_dec_range r/w 5vsb 0 0: 0x80 port will decode all 16-bit address. 1: 0x80 port will decode 15-bit address, ignore lsb. 6 e2h_int_en r/w 5vsb 0 0: disable ec to host interrupt. 1: assert to host (if sirq channel is enabled) when ec to host data available which is set by writing e2c_data register (offset 02h). also assert smi event to pme block when this bit is enabled. 5 e2h_data_avail r/w 5vsb 0 this bit is set when c write data to offset 02h and is clear by host reading the corresponding data. (h2e bass + 02h) 4 h2e_data_avail r 5vsb 0 this bit is set when host write data to offset 01h and is clear by c reading the corresponding data. (e2h bass + 01h) 3-2 e2h_data_type r/w 5vsb 0 user defined register to define the type of ec to host data (offset + 02h) 1-0 h2e_data_type r 5vsb 0 user defined register to define the ty pe of host to ec data (offset + 01h)
F81867 dec, 2011 v0.12p 215 host to ec data register ? offset 01h bit name r/w reset default description 7-0 h2e_data r 5vsb 0x00 this is the data written by host to communicate with c. the type of this byte is determined by h2e_data_type. c reads this byte and check the h2e_data_type to decide what action should be done. ec to host data register ? offset 02h bit name r/w reset default description 7-0 e2h_data r/w 5vsb 0x00 this is the data written by c to communicate with host. the type of this byte is determined by e2h_data_type. host reads this byte and check the e2h_data_type to decide what action should be done. port 80 wdt control register ? offset 03h bit name r/w reset default description 7 p80_wdt_to_st r/w 5vsb 0 this bit is written by c to indicate a timeout stat us. host could write ?1? to this bit to clear status. 6 p80_wdt_en r 5vsb 0 host write ?1? to this bit to inform c to enable port 80 wdt function. 5-4 p80_wdt_unit r 5vsb 0 written by host to define the time unit. ex. 00: 100ms. 01: 1 second. 10: 1 minute. 11: 1 hour. 3-0 p80_wdt_pin r 5vsb 0 written by host to define the pins to assert wdt reset signal. port 80 wdt time register ? offset 04h bit name r/w reset default description 7-0 p80_wdt_time r 5vsb 0xff written by host to define the time count of wdt. port 80 wdt code register ? offset 05h bit name r/w reset default description 7-0 p80_wdt_code r 5vsb 0xff written by host to define the code to start wdt. port 80 code register ? offset 06h bit name r/w reset default description 7-0 p80_code r 5vsb 0xff this byte record the data write to port 80 address (default 0x0080). port 80 last code register ? offset 07h bit name r/w reset default description 7-0 p80_last_code r/w 5vsb 0xff c could write the last data of 80 port into this byte to record the last code during current boot up. port 80 base address high byte register ? offset 10h bit name r/w reset default description 7-0 p80_base_h r/w 5vsb 0x00 the 80 port base address high byte.
F81867 dec, 2011 v0.12p 216 port 80 base address low byte register ? offset 11h bit name r/w reset default description 7-0 p80_base_l r/w 5vsb 0x00 the 80 port base address low byte. 7.20.7 embedded flash control (base address 0x1f00, 256 byte) control register1 ? offset 01h bit name r/w reset default description 7 start_cmd w - - write 1 to this bit will start a single byte read or single byte write command 6-2 reserved - - - reserved 1 ifren r/w 5vsb 0 reserved. 0 flash_cmd r/w 5vsb 0 0: read , 1:write status register ? offset 02h bit name r/w reset default description 7-3 reserved - - - reserved 1 timeout_sts r 5vsb 0 this bit indicates that a single byte write command is timeout and failed. 0 cmd_busy r 5vsb 0 this bit indicates the command is still progressing. control register2 ? offset 03h bit name r/w reset default description 7-0 adr_l r/w 5vsb 0 {adr_h, adr_l} is 13-bits address for embedded flash control register3 ? offset 04h bit name r/w reset default description 7-5 reserved - - - reserved 4-0 adr_h r/w 5vsb 0 {adr_h, adr_l} is 13-bits address for embedded flash control register4 ? offset 05h bit name r/w reset default description 7-0 wr_data r/w 5vsb 0 this byte is data for single byte write command. control register5 ? offset 06h bit name r/w reset default description 7-0 rd_data r 5vsb 0 this byte is stores data read by a single byte read command.
F81867 dec, 2011 v0.12p 217 fintek used only register 1 ? offset 07h bit name r/w reset default description 7-0 reserved r/w 5vsb 1 this byte is fintek used only, don?t change the default value fintek used only register 2 ? offset 0fh bit name r/w reset default description 7-0 reserved - - - this byte is fintek used only, don?t write to this byte. 7.20.8 hardware monitor c side register (base address 0x2000, 256 byte) 7.18.8.1 temperature setting configuration register 1 ? offset 01h bit name r/w reset default description 7-3 reserved 0h - 0 reserved 2 power_down r/w 5vsb 0 hardware monitor function power down. 1 fan_start r/w 5vsb 1 set one to enable startup of fan monitoring operations; a zero puts the part in standby mode. 0 v_t_start r/w 5vsb 1 set one to enable startup of temperature and voltage monitoring operations; a zero puts the part in standby mode. protection mode configuration register ? offset 02h bit name r/w reset default description 7 reserved r/w - 0 dummy register. 6 case_beep_en r/w 5vsb 0 0: disable case open event output via beep. 1: enable case open event output via beep. 5-4 ovt_mode r/w 5vsb 0 00: the ovt# will be low active level mode. 01: the ovt# will be low pulse mode. 10: the ovt# will indicate by 1hz led function. 11: the ovt# will indicate by (400/800hz) beep output. 3 reserved r/w - 0 dummy register. 2 case_smi_en r / w 5vsb 0 0: disable case open event output via pme. 1: enable case open event output via pme. 1-0 alert_mode r/w 5vsb 0 00: the alert# will be low active level mode. 01: the alert# will be high active level mode. 10: the alert# will indicate by 1hz led function. 11: the alert# will indicate by (400/800hz) beep output. case open status register ? offset 03h bit name r/w reset default description 7-1 reserved r/w - 0 reserved 0 case_sts r/w vbat 0 case open event status, write 1 to clear if case open event cleared. (this bit is powered by vbat.)
F81867 dec, 2011 v0.12p 218 configuration register ? 2 ? offset 04h bit name r/w reset default description 7 reserved - - - reserved 6 bias_en r/w 5vsb 0 reserved for fintek use only 5-1 reserved r/w - - reserved 0 s3_hm_en r/w 5vsb 0 set 1 to enable monitoring at s3 state. tsi control register1 ? offset 08h bit name r/w reset default description 7-1 tsi_addr r/w 5vsb 26h amd tsi or intel ibex slave address 0 reserved - - - reserved tsi control register2 ? offset 09h bit name r/w reset default description 7-1 smb_addr r/w 5vsb 0 address for i2c master to use a block write command 0 reserved - - - reserved configuration register 3 ? offset 0ah bit name r/w reset default description 7 beta_en2 r/w 5vsb 0 0: disable the t2 beta compensation. 1: enable the t2 beta compensation. 6 beta_en1 r/w 5vsb 0 0: disable the t1 beta compensation. 1: enable the t1 beta compensation. 5 intel_sel r/w 5vsb 1 this bit is used to select amd ts i or intel ibex when tsi_en is set to 1. 0: select amd 1: select intel 4 mxm_mode r/w lreset# 0 reserved. 3-2 vtt_sel r/w 5vsb 0 peci (vtt) voltage selection. 00: vtt is 1.23v 01: vtt is 1.13v 10: vtt is 1.00v 11: vtt is 1.00v 1 tsi_en r/w 5vsb 0 set this bit 1 to enable amd tsi or intel ibex function 0 peci_en r/w lreset# 0 set this bit 1 to enable intel peci function
F81867 dec, 2011 v0.12p 219 peci address register ? offset 0bh bit name r/w reset default description 7-4 cpu_sel r/w 5vsb 0 select the intel cpu socket number. 0000: no cpu presented. peci host will use ping () command to find the cpu address. 0001: cpu is in socket 0, i.e. peci address is 0x30. 0010: cpu is in socket 0, i.e. peci address is 0x31. 0100: cpu is in socket 0, i.e. peci address is 0x32. 1000: cpu is in socket 0, i.e. peci address is 0x33. others are reserved. 3-1 reserved - - 0 reserved. 0 domain1_en r /w 5vsb 0 if the cpu is selected as dual core. set this register 1 to read the temperature of domain1. tcc temp register ? offset 0ch bit name r/w reset default description 7 - 0 tcc_temp r /w 5vsb 8?h55 tcc activation temperature. when peci is enabled, the absolute value of cpu temperature is calculated by the equation: cpu_temp = tcc_temp + peci reading. the range of this register is -128 ~ 127. tsi_offset register ? offset 0dh bit name r/w reset default description 7 - 0 tsi_offset r /w 5vsb 8?h00 this byte is used as the offset to be added to the cpu temperature reading of amd_tsi. the range of this register is -128 ~ 127. configuration register 4 ? offset 0fh bit name r/w reset default description 7-5 reserved - - 0 reserved. 5 reserved r/w - 1 dummy register 4-2 reserved - - 0 reserved. 1-0 dig_rate_sel r/w 5vsb 0 reserved for fintek use only
F81867 dec, 2011 v0.12p 220 tsi temperature 0 ? offset e0h bit name r/w reset default description 7-0 tsi_temp0 r / w 5vsb - this is the amd tsi reading if amd tsi enable. and will be highest temperatur e among cpu, mch and pch if intel temperature interface enable. the range is 0~255 o c. to access this byte, mch_bank_sel must set to ?0?. i2c_data0 r /w 5vsb 8?h00 this byte is used as multi-purpose: 7. the received data of receive protocol. 8. the first received byte of read word protocol. 9. the 10 th received byte of read block protocol. 10. the sent data for send byte protocol and write byte protocol. 11. the first send byte for write word protocol. 12. the first send byte for write block protocol. to access this byte, mch_ban k_sel should be set to ?1?. tsi temperature 1 ? offset e1h bit name r/w reset default description 7-0 tsi_temp1 r 5vsb - this is the high byte of intel temperature interf ace pch reading. the range is 0~255 o c. to access this byte, mch_ban k_sel should be set to ?0?. i2c_data1 r /w 5vsb 8?h00 this byte is used as multi-purpose: 5. the second received byte of read word protocol. 6. the 11 th received byte of read block protocol. 7. the second send byte for write word protocol. 8. the second send byte fo r write block protocol. to access this byte, mch_ban k_sel should be set to ?1?. tsi temperature 2 low byte ? offset e2h bit name r/w reset default description 7 - 0 tsi_temp2_lo r 5vsb - this is the low byte of intel temperature interface cpu reading. the reading is the fraction part of cpu temperature. bit 0 indicates the error status. 0: no error. 1: error code. to access this byte, mch_ban k_sel should be set to ?0?.
F81867 dec, 2011 v0.12p 221 i2c_data2 r /w 5vsb 8?h00 this is the 12 th byte of the block read protocol. this byte is also used as the 3rd byte of block write protocol. to access this byte, mch_ban k_sel should be set to ?1?. tsi temperature 2 high byte ? offset e3h bit name r/w reset default description 7-0 tsi_temp2_hi r 5vsb - this is the high byte of intel te mperature interface cpu reading. the reading is the decimal part of cpu temperature. to access this byte, mch_ban k_sel should be set to ?0?. i2c_data3 r /w 5vsb 8?h00 this is the 13 th byte of the block read protocol. this byte is also used as the 4t h byte of block write protocol. to access this byte, mch_ban k_sel should be set to ?1?. tsi temperature 3 ? offset e4h bit name r/w reset default description 7-0 tsi_temp3 r 5vsb - this is the high byte of intel temperature interf ace mch reading. the range is 0~255 o c. to access this byte, mch_ban k_sel should be set to ?0?. i2c_data4 r /w 5vsb 8?h00 this is the 14 th byte of the block read protocol. this byte is also used as the 5t h byte of block write protocol. to access this byte, mch_ban k_sel should be set to ?1?. tsi temperature 4 ? offset e5h bit name r/w reset default description 7-0 tsi_temp4 r 5vsb - this is the high byte of intel temperature interface dimm0 reading. the range is 0~255 o c. to access this byte, mch_ban k_sel should be set to ?0?. i2c_data5 r /w 5vsb 8?h00 this is the 15 th byte of the block read protocol. this byte is also used as the 6t h byte of block write protocol. to access this byte, mch_ban k_sel should be set to ?1?. tsi temperature 5 ? offset e6h bit name r/w reset default description 7-0 tsi_temp5 r 5vsb - this is the high byte of intel temperature interface dimm1 reading. the range is 0~255 o c. to access this byte, mch_ban k_sel should be set to ?0?.
F81867 dec, 2011 v0.12p 222 i2c_data6 r /w 5vsb 8?h00 this is the 16 th byte of the block read protocol. this byte is also used as the 7t h byte of block write protocol. to access this byte, mch_ban k_sel should be set to ?1?. tsi temperature 6 ? offset e7h bit name r/w reset default description 7-0 tsi_temp6 r 5vsb - this is the high byte of intel temperature interface dimm2 reading. the range is 0~255 o c. to access this byte, mch_ban k_sel should be set to ?0?. i2c_data7 r /w 5vsb 8?h00 this is the 17 th byte of the block read protocol. this byte is also used as the 8t h byte of block write protocol. to access this byte, mch_ban k_sel should be set to ?1?. tsi temperature 7 ? offset e8h bit name r/w reset default description 7-0 tsi_temp7 r 5vsb - this is the high byte of intel temperature interface dimm3 reading. the range is 0~255 o c. the above 9 bytes could also be used as the read data of block read protocol if the tsi is disable or pending. i2c_data8 r /w 5vsb 8?h00 this is the 18 th byte of the block read protocol. this byte is also used as the 9t h byte of block write protocol. to access this byte, mch_ban k_sel should be set to ?1?. i2c data buffer 9 ? offset e9h bit name r/w reset default description 7 - 0 i2c_data9 r /w 5vsb ffh this is the 18 th byte of the block read protocol. this byte is also used as the 9t h byte of block write protocol. to access this byte, mch_ban k_sel should be set to ?1?. block write count register ? offset ech bit name r/w reset default description 7 mch_bank_sel r /w 5vsb 0 this bit is used to select the register in offset e0h to e9h. set ?0? to read the temperature bank and ?1? to access the data bank. 6 reserved - - 0 reserved 5 - 0 block_wr_cnt r /w 5vsb 0 use the register to specify the byte count of block write protocol. support up to 10 bytes.
F81867 dec, 2011 v0.12p 223 i2c command byte/tsi co mmand byte ? offset edh bit name r/w reset default description 7 - 0 i2c_cmd/tsi_cmd r /w 5vsb 0/1 there are actual two bytes for this offset. tsi_cmd_prog select which byte to be programmed: 0: i2c_cmd, which is the command code for write byte/word, read byte/word, block write/r ead and process call protocol. 1: tsi_cmd, which is the command code for intel temperature interface block read protocol and the data byte for amd tsi send byte protocol. i2c status ? offset eeh bit name r/w reset default description 7 tsi_pending r /w lreset# 0 set 1 to pending auto tsi accessing. (in amd model, auto accessing will issue a send-byte followed a receive-byte; in intel model, auto accessing will issue a block read). to use the scl/ sda as a i2c master, set this bit to ?1? first. 6 tsi_cmd_prog r /w 5vsb 0 set 1 to program tsi_cmd. 5 proc_kill r/w 5vsb 0 kill the current i2c transfer and return the state machine to idle. it will set an fail status if the cu rrent transfer is not completed. 4 fail_sts r 5vsb 0 this is set when proc_ki ll k ill an un-completed transfer. it will be auto cleared by next i2c transfer. 3 i2c_abt_err r 5vsb 0 this is the arbitration lost status if a i2c command is issued. auto cleared by next i2c command. 2 i2c_to_err r 5vsb 0 this is the timeout status if a i2c command is issued. auto cleared by next i2c command. 1 i2c_nac_err r 5vsb 0 this is the nack error status if a i2c command is issued. auto cleared by next i2c command. 0 i2c_ready r 5vsb 1 0: a i2c transfer is in process. 1: ready for next i2c command. i2c protocol select ? offset efh bit name r/w reset default description 7 i2c_start w - 0 write ?1? to trigger a i2c transfer with the protocol specified by smb_protocol. 6 - 4 reserved - - - reserved.
F81867 dec, 2011 v0.12p 224 3 - 0 i2c_protocol r /w 5vsb 0 select what protocol if a i2c transfer is triggered. 0001b: send byte. 0010b: write byte. 0011b: write word. 0100b: reserved. 0101b: block write. 0111b: quick command (write). 1001b: receive byte. 1010b: read byte. 1011b: reserved 1101b: block read. 1111b: reserved otherwise: reserved. 7.18.8.2 peci 3.0 & temperature setting peci 3.0 command and register peci configuration register ? offset 40h bit name r/w reset default description 7 r diamsr_cmd_e n r/w 5vsb 0 when peci temperature monitoring is enabled, set this bit 1 will generate a rdiamsr() command before a gettemp() command. 6 c3_update_en r/w 5vsb 0 if rdiamsr_cmd_en is not set to 1, the temperature data is not allowed to be updated when the completion code of rdiamsr() is 0x82. 5-4 reserved r - - reserved 3 c3_ptemp_en r/w 5vsb 0 set this bit 1 to enable updateing positive value of temperature if the completion code of rdiamsr() is 0x82. 2 c0_ptemp_en r/w 5vsb 0 set this bit 1 to enable updating positive value of temperature if the completion code of rdiamsr() is not 0x82 and the bit 8 of completion code is not 1 either. 1 c3_all0_en r/w 5vsb 0 set this bit 1 to enable updating temperature value 0x0000 if the completion code of rdiamsr() is 0x82. 0 c0_all0_en r/w 5vsb 0 set this bit 1 to enable updating temperature value 0x0000 if the completion code of rdiamsr() is not 0x82 and the bit 8 of completion code is not 1 either. peci master control register ? offset 41h bit name r/w reset default description 7 peci_cmd_star t w 5vsb - write 1 to this bit to start a peci command when using as a peci master. (peci_pending must be set to 1) 6-5 reserved r - - reserved 4 peci_pending r/w 5vsb 0 set this bit 1 to stop monitoring peci temperature. 3 reserved r - - reserved
F81867 dec, 2011 v0.12p 225 2-0 peci_cmd r/w 5vsb 3?h0 peci command to be used by peci master. 000: ping() 001: getdib() 010: gettemp() 011: rdiamsr() 100: rdpkgconfig() 101: wrpkgconfig() others: reserved peci master status register ? offset 42h bit name r/w reset default description 7-3 reserved r - - reserved 2 abort_fcs r/wc 5vsb - this bit is the abort fcs status of peci master commands. write this bit 1 or read this byte will clear this bit to 0. 1 peci_fcs_err r/wc 5vsb - this bit is the fcs error status of peci master commands. write this bit 1 or read this byte will clear this bit to 0. 0 peci_finish r/wc 5vsb - this bit is the command finish status of peci master commands. write this bit 1 or read this byte will clear this bit to 0. peci master data0 register ? offset 43h bit name r/w reset default description 7-0 peci_data0 r/w 5vsb 0 for rdiamsr(), rdpkgconfig() and wrpkgconfig() command, this byte represents ?host id[7:1 ] & retry[0]?. please refer to peci interface specificat ion for more detail. peci master data1 register ? offset 44h bit name r/w reset default description 7-0 peci_data1 r/w 5vsb 0 for rdiamsr() , this byte represents ?processor id?. for rdpkgconfig() and wrpkgconfig() , this byte represents ?offset?. please refer to peci interface specification for more detail. peci master data2 register ? offset 45h bit name r/w reset default description 7-0 peci_data2 r/w 5vsb 0 for rdiamsr(), this byte is the least significant byte of ?msr address?. for rdpkgconfig() and wrpkgconfig(), this byte is the least significant byte of ?parameter?. please refer to peci interface specification for more detail. peci master data3 register ? offset 46h bit name r/w reset default description 7-0 peci_data3 r/w 5vsb 0 for rdiamsr(), this byte is the most significant byte of ?msr address?. for rdpkgconfig() and wrpkgconfig(), this byte is the most significant byte of ?parameter?. please refer to peci interface specification for more detail.
F81867 dec, 2011 v0.12p 226 peci master data4 register ? offset 47h bit name r/w reset default description 7-0 peci_data4 r/w 5vsb 0 for getdib() , this byte represents ?device info? for gettemp(), this byte represents the least significant byte o f temperature. for rdiamsr() and rdpkgconfig() , this byte is ?completion code?. for wrpkgconfig(), this byte represents ?data[7:0]? peci master data5 register ? offset 48h bit name r/w reset default description 7-0 peci_data5 r/w 5vsb 0 for getdib() , this byte represents ?revision number? for gettemp(), this byte represen ts the most significant byte o f temperature. for rdiamsr() and rdpkgconfig() , this byte represents ?data[7:0]? for wrpkgconfig(), this byte represents ?data[15:8]? peci master data6 register ? offset 49h bit name r/w reset default description 7-0 peci_data6 r/w 5vsb 0 for rdiamsr() and rdpkgconfig() , this byte represents ?data[15:8]?. for wrpkgconfig(), this byte represents ?data[23:16]? peci master data7 register ? offset 4ah bit name r/w reset default description 7-0 peci_data7 r/w 5vsb 0 for rdiamsr() and rdpkgconfig() , this byte represents ?data[23:16]?. for wrpkgconfig(), this byte represents ?data[31:24]? peci master data8 register ? offset 4bh bit name r/w reset default description 7-0 peci_data8 r/w 5vsb 0 for rdiamsr() and rdpkgconfig() , this byte represents ?data[31:24]?. for wrpkgconfig(), this byte represents ?aw fcs? peci master data9 register ? offset 4ch bit name r/w reset default description 7-0 peci_data9 r/w 5vsb 0 for rdiamsr(), this byte represents ?data[39:32]?. for wrpkgconfig(), this byte represents ?completion code? peci master data10 register ? offset 4dh bit name r/w reset default description 7-0 peci_data10 r/w 5vsb 0 for rdiamsr(), this byte represents ?data[47:40]?.
F81867 dec, 2011 v0.12p 227 peci master data11 register ? offset 4eh bit name r/w reset default description 7-0 peci_data11 r/w 5vsb 0 for rdiamsr(), this byte represents ?data[55:48]?. peci master data12 register ? offset 4fh bit name r/w reset default description 7-0 peci_data12 r/w 5vsb 0 for rdiamsr(), this byte represents ?data[63:56]?. hm manual control register1 ? offset 50h bit name r/w reset default description 7 load_ch w - - write 1 to load a temperature or voltage channel to be converted 6 stop_ch r/w 5vsb 0 set to 1 when load a channel will generate a one-shot conversion. 5 hold_ch r/w 5vsb 0 set to 1 when load a channel will keep converting this channel. 4:0 channel r/w 5vsb 0 first channel to be converted when load_ch is set to 1. 00000: vcc 00001: vin1 00010: vin2 00011: vin3 00100: vin4 00101: vsb3v 00110: vbat 00111: vsb5v 10000: intel peci 10001: t1 10010: t2 11000: amd tsi/intel ibex hm manual control status register 1 ? offset 51h bit name r/w reset default description 7 reserved - - - reserved 6 v_conv_sts r 5vsb - at least one of the voltage channels had finish converting. 5 peci_conv_sts wc 5vsb - peci channel had finish converting 4 tsi_conv_sts wc 5vsb - tsi channel had finish converting 3 reserved - - reserved 2 t2_conv_sts w c 5vsb - t2 channel had finish converting 1 t1_conv_sts w c 5vsb - t1 channel had finish converting 0 reserved - - reserved hm manual control status register 2 ? offset 52h bit name r/w reset default description 7 vsb5v_conv_sts w c 5vsb - vsb5v voltage channel had finish converting 6 vbat_conv_sts wc 5vsb - vbat voltage channel had finish converting 5 vsb3v_conv_st s wc 5vsb - vsb3v voltage channel had finish converting
F81867 dec, 2011 v0.12p 228 4 vin4_conv_sts wc 5vsb - vin4 voltage channel had finish converting 3 vin3_conv_sts wc 5vsb - vin3 voltage channel had finish converting 2 vin2_conv_sts wc 5vsb - vin2 voltage channel had finish converting 1 vin1_conv_sts wc 5vsb - vin1 voltage channel had finish converting 0 vcc_conv_sts w c 5vsb - vcc voltage channel had finish converting hm c interrupt enable register 1 ? offset 53h bit name r/w reset default description 7 - 6 reserved - - - reserved 5 peci_int_en r/w 5vsb 0 generate an interrupt for c when this bit is set to 1 and peci _conv_sts is 1. 4 tsi_int_en r/w 5vsb 0 generate an interrupt for c when this bit is set to 1 and tsi_conv_sts is 1. 3 reserved - - - reserved 2 t2_int_en r/w 5vsb 0 generate an interrupt for c when this bit is set to 1 and t2_conv_sts is 1. 1 t1_int_en r/w 5vsb 0 generate an interrupt for c when this bit is set to 1 and t1_conv_sts is 1. 0 t0_int_en r/w 5vsb 0 generate an interrupt for c when this bit is set to 1 and t0_conv_sts is 1. hm c interrupt enable register 2 ? offset 54h bit name r/w reset default description 7 vsb5v_int_en r /w 5vsb 0 generate an interrupt for c when this bit is set to 1 and vsb5v _conv_sts is 1. 6 vbat_int_en r/w 5vsb 0 generate an interrupt for c when this bit is set to 1 and vbat _conv_sts is 1. 5 vsb3v_int_en r/w 5vsb 0 generate an interrupt for c when this bit is set to 1 and vsb 3v_conv_sts is 1. 4 vin4_int_en r/w 5vsb 0 generate an interrupt for c when this bit is set to 1 and vin4 _conv_sts is 1. 3 vin3_int_en r/w 5vsb 0 generate an interrupt for c when this bit is set to 1 and vin3 _conv_sts is 1. 2 vin2_int_en r/w 5vsb 0 generate an interrupt for c when this bit is set to 1 and vin2 _conv_sts is 1. 1 vin1_int_en r/w 5vsb 0 generate an interrupt for c when this bit is set to 1 and vin1 _conv_sts is 1. 0 vcc_int_en r /w 5vsb 0 generate an interrupt for c when this bit is set to 1 and vcc _conv_sts is 1. hm raw data register 1 ? offset 55h bit name r/w reset default description 7 - 0 raw_data_l r 5vsb 0 low byte of hm converting raw data hm raw data register 2 ? offset 56h bit name r/w reset default description 7 - 2 reserved - - - reserved
F81867 dec, 2011 v0.12p 229 1 - 0 raw_data_h r 5vsb 0 the highest two bits of hm converting raw data temperature register temperature pme# enable register ? offset 60h bit name r/w reset default description 7 reserved r/w - 0 reserved 6 en_ t2_ovt_pme r/w 5vsb 0 if set this bit to 1, pme# signal will be issued when temp2 exceeds ovt setting. 5 en_ t1_ovt_pme r/w 5vsb 0 if set this bit to 1, pme# signal will be issued when temp1 exceeds ovt setting. 4 en_ t0_ ovt_pme r/w 5vsb 0 if set this bit to 1, pme# signal will be issued when temp0 exceeds ovt setting. 3 reserved r/w - 0 reserved 2 en_ t2_exc_pme r/w 5vsb 0 if set this bit to 1, pme# signal will be issued when temp2 exceeds high limit setting. 1 en_ t1_exc_pme r/w 5vsb 0 if set this bit to 1, pme# signal will be issued when temp1 exceeds high limit setting. 0 en_ t0_exc_pme r/w 5vsb 0 if set this bit to 1, pme# signal will be issued when temp0 exceeds high limit setting. temperature interrupt status register ? offset 61h bit name r/w reset default description 7 reserved r/w - 0 reserved 6 t2_ovt _sts r/w 3vcc 0 this bit gets 1 to indicate temp2 temperature sensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. write 1 to clear this bit, write 0 to ignore. 5 t1_ovt _sts r/w 3vcc 0 this bit gets 1 to indicate temp1 temperature sensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. write 1 to clear this bit, write 0 to ignore. 4 t0_ovt _sts r/w 3vcc 0 a one indicates temp0 temperature sensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. write 1 to clear this bit, write 0 will be ignored. 3 reserved r/w - 0 reserved 2 t2_exc _sts r/w 3vcc 0 this bit gets 1 to indicate temp2 temperature sensor has exceeded high limit or below the ?high limit ?hysteresis? limit. write 1 to clear this bit, write 0 to ignore. 1 t1_exc _sts r/w 3vcc 0 this bit gets 1 to indicate temp1 temperature sensor has exceeded high limit or below the ?high limit ?hysteresis? limit. write 1 to clear this bit, write 0 to ignore. 0 t0_exc _sts r/w 3vcc 0 a one indicates temp0 temperature sensor has exceeded high limit or below the ?high limit ?hysteresis? limit. write 1 to clear this bit, write 0 will be ignored.
F81867 dec, 2011 v0.12p 230 temperature real time status register ? offset 62h bit name r/w reset default description 7 reserved r/w - 0 reserved 6 t2_ovt r/w 3vcc 0 set when the temp2 exceeds the ovt limit. clear when the temp2 is below the ?ovt limit ?hysteresis? temperature. 5 t1_ovt r/w 3vcc 0 set when the temp1 exceeds the ovt limit. clear when the temp1 is below the ?ovt limit ?hysteresis? temperature. 4 t0_ovt r/w 3vcc 0 set when the temp0 exceeds the ovt limit. clear when the temp0 is below the ?ovt limit ?hysteresis? temperature. 3 reserved r/w - 0 reserved 2 t2_exc r/w 3vcc 0 set when the temp2 exceeds the high limit. clear when the temp2 is below the ?high limit ?hysteresis? temperature. 1 t1_exc r/w 3vcc 0 set when the temp1 exceeds the high limit. clear when the temp1 is below the ?high limit ?hysteresis? temperature. 0 t0_exc r/w 3vcc 0 set when the temp0 exceeds the high limit. clear when the temp0 is below the ?high limit ?hysteresis? temperature. temperature beep enable register ? offset 63h bit name r/w reset default description 7 reserved r/w - 0 reserved 6 en_ t2_ ovt_beep r/w 5vsb 0 if set this bit to 1, beep signal will be issued when temp2 exceeds ovt limit setting. 5 en_ t1_ ovt_beep r/w 5vsb 0 if set this bit to 1, beep signal will be issued when temp1 exceeds ovt limit setting. 4 en_ t0_ ovt_beep r/w 5vsb 0 if set this bit to 1, beep signal will be issued when temp0 exceeds ovt limit setting. 3 reserved r/w - 0 reserved 2 en_ t2_exc_beep r/w 5vsb 0 if set this bit to 1, beep signal will be issued when temp2 exceeds high limit setting. 1 en_ t1_exc_beep r/w 5vsb 0 if set this bit to 1, beep signal will be issued when temp1 exceeds high limit setting. 0 en_ t0_exc_beep r/w 5vsb 0 if set this bit to 1, beep signal will be issued when temp0 exceeds high limit setting. t1 ovt and high limit temperature select register ? offset 64h bit name r/w reset default description 7-6 reserved r/w - 0 reserved
F81867 dec, 2011 v0.12p 231 5-4 ovt_temp_sel r/w 5vsb 0 select the source temperature for t1 ovt limit. 0: select t1 to be compared to temperature 1 ovt limit. 1: select cpu temperature fr om peci to be compared to temperature 1 ovt limit. 2: select cpu temperature from amd tsi or intel pch i2c to be compared to temperature 1 ovt limit. 3: select the max temperature from intel pch i2c to be compared to temperature 1 ovt limit. 3-2 reserved r/w - 0 reserved 1-0 high_ temp_sel r/w 5vsb 0 select the source temperature for t1 high limit. 0: select t1 to be compared to temperature 1 high limit. 1: select cpu temperature fr om peci to be compared to temperature 1 high limit. 2: select cpu temperature from amd tsi or intel pch i2c to be compared to temperature 1 high limit. 3: select the max temperature from intel pch i2c to be compared to temperature 1 high limit. ovt and alert output enable register 1 ? offset 66h bit name r/w reset default description 7 reserved r/w - 0 reserved 6 en_t2_alert r/w 5vsb 0 enable temperature 2 alert event (asserted when temperature over high limit) 5 en_t1_alert r/w 5vsb 0 enable temperature 1 alert event (asserted when temperature over high limit) 4 en_t0_alert r/w 5vsb 0 enable temperature 0 alert ev ent (asserted when temperature over high limit) 3 reserved - - 0 reserved 2 en_t2_ovt r/w 5vsb 0 enable over temperature (ovt) mechanism of temperature2. 1 en_t1_ovt r/w 5vsb 1 enable over temperature (ovt) mechanism of temperature1. 0 en_t0_ovt r/w 5vsb 0 enable over temperature (ovt) mechanism of temperature0. reserved ? offset 67~69h bit name r/w reset default description 7 - 0 reserved - - - reserved
F81867 dec, 2011 v0.12p 232 temperature sensor type register ? offset 6bh bit name r/w reset default description 7-4 reserved ro - 0 reserved 3 reserved ro - 0 reserved 2 t2_mode r/w 5vsb 1 0: temp2 is connected to a thermistor. 1: temp2 is connected to a bjt. (default) 1 t1_mode r/w 5vsb 1 0: temp1 is connected to a thermistor 1: temp1 is connected to a bjt.(default) 0 reserved r - 0 reserved temp1 limit hystersis select register ? offset 6ch bit name r/w reset default description 7-4 temp1_hys r/w 5vsb 4h limit hysteresis. (0~15 o c) temperature and below the (boundary ? hysteresis). 3-0 temp0_hys r/w 5vsb 4h limit hysteresis. (0~15 o c) temperature and below the (boundary ? hysteresis). temp2 and temp3 limit hyst ersis select register ? offset 6dh bit name r/w reset default description 7-4 reserved r - 0 reserved 3-0 temp2_hys r/w 5vsb 4h limit hysteresis. (0~15 degree c) temperature and below the ( boundary ? hysteresis ). diode open status register ? offset 6fh bit name r/w reset default description 7-6 reserved r - - reserved 5 peci_open r 3vcc - when peci interface is enabled, ?1? indicates an error code (0x0080 or 0x0081) is received from peci slave. 4 tsi_open r 3vcc - when tsi interface is enabled, ?1? indicates the error of not receiving nack bit or a timeout occurred. 3 reserved r - - reserved 2 t2_diode_open r 3vcc - ?1? indicates external diode 2 is open or short 1 t1_diode_open r 3vcc - ?1? indicates external diode 1 is open or short 0 t0_diode_open ro 3vcc - this register indicates the abnormality of temperature 0 measurement.
F81867 dec, 2011 v0.12p 233 temperature ? offset 70h- 8dh address attribute reset default value description 70h ro 3vcc -- temperature 0 reading. the unit of reading is 1 o c.at the moment of reading this register. 71h reserved 3vcc ffh reserved 72h r 3vcc -- temperature 1 reading. the unit of reading is 1oc.at the moment of reading this register. 73h r 3vcc -- reserved 74h r 3vcc -- temperature 2 reading. the unit of reading is 1oc.at the moment of reading this register. 75-79h r 3vcc -- reserved 7ah r 3vcc -- the data of cpu temperature from digital interface after iir filter. (available if intel ibx or amd tsi interface is enabled) 7bh r 3vcc -- the raw data of pch temperature from digital interface. (only available if intel ibx interface is enabled) 7ch r 3vcc -- the raw data of mch read from digital interface. (only available if intel ibx interface is enabled) 7dh r 3vcc -- the raw data of maximum temperature between cpu/pch/mch from digital inte rface. (only available if intel ibx interface is enabled) 7eh r 3vcc -- the data of cpu temperature from digital interface after iir filter. (only available if peci interface is enabled) 80h r/w 5vsb 64h temperature sensor 0 ovt limit. the unit is 1 o c. 81h r/w 5vsb 55h temperature sensor 0 high limit. the unit is 1 o c. 82h r/w 5vsb 64h temperature sensor 1 ovt limit. the unit is 1 o c. 83h r/w 5vsb 55h temperature sensor 1 high limit. the unit is 1 o c. 84h r/w 5vsb 64h temperature sensor 2 ovt limit. the unit is 1 o c. 85h r/w 5vsb 55h temperature sensor 2 high limit. the unit is 1 o c. 86-8bh r -- -- reserved 8c~8dh r -- ffh reserved t1 slope adjust register ? offset 7fh bit name r/w reset default description 7-4 reserved - - - reserved 3 t1_add r/w 5vsb 0h this bit is the sign bit for t1 reading slope adjustment. see t1_scale below for detail.
F81867 dec, 2011 v0.12p 234 2-0 t1_scale r/w - 0h t1_add t1_scale slope x 00 no adjustment 0 01 15/16 0 10 31/32 0 11 63/64 1 01 17/16 1 10 33/32 1 11 65/64 temperature filter select register ? offset 8eh bit name r/w reset default description 7-6 iir-queur0 r/w 5vsb 2?b10 the queue time for second filter to quickly update values. 00: 8 times. 01: 12 times. 10: 16 times. (default) 11: 24 times. 5-4 iir-queur2 r/w 5vsb 2?b10 the queue time for second filter to quickly update values. 00: 8 times. 01: 12 times. 10: 16 times. (default) 11: 24 times. 3-2 iir-queur1 r/w 5vsb 2?b10 the queue time for second filter to quickly update values. 00: 8 timers. 01: 12 times. 10: 16 times. (default) 11: 24 times. 1-0 iir-queur_dig r/w 5vsb 2?b10 the queue time for second filter to quickly update values. (for cpu temperature from peci or tsi interface) 00: 8 timers. 01: 12 times. 10: 16 times. (default) 11: 24 times. 7.18.8.3 voltage setting voltage-protect shut down enable register ? offset 10h bit name r/w reset default description 7 reserved - - 0 reserved. 6 v3_vp_en r/w vbat* 0 voltage-protect shut down enable for vin3 5 v2_vp_en r/w vbat* 0 voltage-protect enable for vin2
F81867 dec, 2011 v0.12p 235 4-1 reserved - - 0 reserved 0 v0_vp_en r/w vbat* 0 voltage-protect shut down enable for 3vcc voltage-protect status register (powered by vbat) ? offset 11h bit name r/w reset default description 7-6 reserved - - 0 reserved. 0 v_exc_vp r/w c vbat/ 5vsb* 0 this bit is voltage-protect status. once one of the monitored voltages (3vcc, vin5, vin6) over its related over-voltage limits or under its related under-voltage limits and if the related voltage-protect shut down enable bit is set, this bit will be set to 1. write a 1 to this bit will clear it to 0. (this bit is powered by vbat) * reset by vbat when ovp_mode is ?0?, reset by 5vsb when ovp_mode is ?1? voltage-protect configuration register ? offset 12h bit name r/w reset default description 7-4 reserved - - - reserved. 3-2 pu_time r/w vbat 2?h1 pson# de-active time select for voltage protection. 00: pson# tri-state 0.5 sec and then inverted of s3# when over voltage or under voltage occurs. 01: pson# tri-state 1 sec and t hen inverted of s3# when over voltage or under voltage occurs. 10: pson# tri-state 2 sec and t hen inverted of s3# when over voltage or under voltage occurs. 11: pson# tri-state 4 sec and then inverted of s3# when over voltage or under voltage occurs. 1-0 vp_en_delay r/w vbat 2?h2 vp_en_delay could set the delay time to start voltage protecting after vdd power is ok when ovp_mode is 1. (ovp_mode is strapped by rts1# pin) 00: bypass 01: 50ms 10: 100ms 11: 200ms voltage1 pme# enable register ? offset 14h bit name r/w reset default description 7-2 reserved - - 0 reserved
F81867 dec, 2011 v0.12p 236 1 en_v1_pme r/w 5vsb 0 a one enables the corresponding interrupt status bit for pme# interrupt. set this bit 1 to enable pme# function for vin1. 0 reserved - - - reserved voltage1 interrupt status register ? offset 15h bit name r/w reset default description 7-2 reserved -- - 0 reserved 1 v1_ exc _sts r/w 5vsb 0 this bit is set when the vin1 is over the high limit. write 1 to clear this bit, write 0 will be ignored. 0 reserved - - - reserved voltage1 exceeds real time status register 1 ? offset 16h bit name r/w reset default description 7-2 reserved -- - 0 reserved 1 v1_exc ro 5vsb 0 a one indicates vin1 exceeds the high or low limit. a zero indicates vin1 is in the safe region. 0 reserved -- - 0 reserved voltage1 beep enable register ? offset 17h bit name r/w reset default description 7-2 reserved -- - 0 reserved 1 en_v1_beep r/w 5vsb 0 a one enables the corresponding interrupt status bit for beep output of vin1. 0 reserved -- - 0 reserved voltage protection power good select register ? offset 3fh bit name r/w reset default description 7-1 reserved -- - 0 reserved 0 ovp_rst_sel r/w vbat 0 0: ovp/uvp power good signal is 3vccok (3vcc > 2.8v) 1: ovp/uvp power good signal is pwrok. ovp/uvp function wont? star t detecting until power good. voltage reading and limit ? offset 20h- 4fh address attribute reset default value description 20h r 3vcc -- 3vcc reading. the unit of reading is 8mv. 21h r 3vcc -- vin1 (vcore) reading. the unit of reading is 8mv. 22h r 3vcc -- vin2 reading. the unit of reading is 8mv. 23h r 3vcc -- vin3 reading. the unit of reading is 8mv. 24h r 3vcc -- vin4 reading. the unit of reading is 8mv.
F81867 dec, 2011 v0.12p 237 25h r 3vcc -- vsb3v reading. the unit of reading is 8mv. 26h r 3vcc -- vbat reading. the unit of reading is 8mv. 27h r 3vcc -- vsb5v reading. the unit of reading is 8 mv. the vsb5v voltage to be monitored is internally divided by 3. 28h-2ch r -- ff reserved 2dh ro 3vcc -- fan1 present fan duty reading 2eh ro 3vcc -- fan2 present fan duty reading 2fh ro 3vcc -- fan3 present fan duty reading 30 ro vbat 89 3vcc under-voltage protection limit. the unit is 8mv 31 r/w vbat f2 3vcc over-voltage protection limit. the unit is 8 mv 32~35h r ff reserved 36h r/w vbat e2 vin2 over-voltage limit (v2_ovv_limit). the unit is 8mv. (this byte is powered by vbat.) 37h r/w vbat e1 vin3 over-voltage limit (v3_ovv_limit). the unit is 8mv. (this byte is powered by vbat.) 38h r/w vbat 83 vin2 under-voltage limit (v2_uvv_limit). the unit is 8mv (this byte is powered by vbat) 39h r/w vbat 96 vin3 under-voltage limit (v3_uvv_limit). the unit is 8mv (this byte is powered by vbat) 3a r/w 5vsb ff v1 high limit setting register. the unit is 8mv. 3b~3f ro ff reserved. 7.18.8.4 fan control setting fan pme# enable register ? offset 90h bit name r/w reset default description 7-3 reserved r - 0 reserved 2 en_fan3_pme r/w 5vsb 0 a one enables the corresponding interrupt status bit for pme# interrupt set this bit 1 to enable pme# function for fan3. 1 en_fan2_pme r/w 5vsb 0 a one enables the corresponding interrupt status bit for pme# interrupt. set this bit 1 to enable pme# function for fan2. 0 en_fan1_pme r/w 5vsb 0 a one enables the corresponding interrupt status bit for pme# interrupt. set this bit 1 to enable pme# function for fan1.
F81867 dec, 2011 v0.12p 238 fan interrupt status register ? offset 91h bit name r/w reset default description 7-3 reserved r - 0 reserved 2 fan3_sts r/w 3vcc -- this bit is set when the fan3 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. 1 fan2_sts r/w 3vcc -- this bit is set when the fan2 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. 0 fan1_sts r/w 3vcc -- this bit is set when the fan1 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. fan real time status register ? offset 92h bit name r/w reset default description 7-3 reserved -- - 0 reserved 2 fan3_exc r 3vcc -- this bit set to high mean that fan3 count can?t meet expect count over than smi time(cr9f) or when duty not zero but fan stop over then 3 sec. 1 fan2_exc r 3vcc -- this bit set to high mean that fan2 count can?t meet expect count over than smi time(cr9f) or when duty not zero but fan stop over then 3 sec. 0 fan1_exc r 3vcc -- this bit set to high mean that fan1 count can?t meet expect count over than smi time(cr9f) or when duty not zero but fan stop over then 3 sec. fan beep# enable register ? offset 93h bit name r/w reset default description 7 reserved - - - reserved 6 full_with_ t2_en r/w 5vsb 0 set one will enable fan to force full speed when t2 over high limit. 5 full_with_ t1_en r/w 5vsb 0 set one will enable fan to force full speed when t1 over high limit. 4 reserved - - - reserved 3 reserved - - - reserved. 2 en_fan3_ beep r/w 5vsb 0 a one enables the corr esponding interrupt status bit for beep. 1 en_fan2_ beep r/w 5vsb 0 a one enables the corr esponding interrupt status bit for beep. 0 en_fan1_ beep r/w 5vsb 0 a one enables the corr esponding interrupt status bit for beep.
F81867 dec, 2011 v0.12p 239 fan type select register ? offset 94h fan_prog_sel = 0 bit name r/w reset default description 7-6 reserved - - - reserved. 5-4 fan3_type r/w 3vcc 2?b 0s 00: output pwm mode (push pull) to control fans. 01: use linear fan application circui t to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: reserved. bit 0 is power on trap by fanctrl3 0: fanctrl3 is pull up by external resistor. 1: fanctrl3 is pull down by internal 100k resistor. 3-2 fan2_type r/w 3vcc 2?b 0s 00: output pwm mode (push pull) to control fans. 01: use linear fan application circui t to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: reserved. bit 0 is power on trap by fanctrl2 0: fanctrl2 is pull up by external resistor. 1: fanctrl2 is pull down by internal 100k resistor. 1-0 fan1_type r/w 3vcc 2?b 0s 00: output pwm mode (push pull) to control fans. 01: use linear fan application circui t to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: reserved. bit 0 is power on trap by fanctrl1 0: fanctrl1 is pull up by external resistor. 1: fanctrl1is pull down by internal 100k resistor. s : register default values are decided by trapping.
F81867 dec, 2011 v0.12p 240 fan1 base temperature register ? offset 94h (fan_prog_sel = 1) bit name r/w reset default description 7-0 fan1_base _temp r/w 5vsb 0 this register is used to set the base temperature for fan1 temperature adjustment. the fan1 temperature is calculated according to the equation: tfan1 = tnow + (ta ? tb)*ct where tnow is selected by fan1_temp_sel_dig and fan1_temp_sel. tb is this register, ta is selected by tfan1_adj_sel and ct is selected by tfan1_adj_up_rate/tfan1_adj_dn_rate. to access this register, fan_ prog_sel(cr9f[7]) must set to ?1?. fan1 temperature adjust rate register ? offset 95h (fan_prog_sel = 1) bit name r/w reset default description 7 reserved - - - reserved 6-4 tfan1_adj_up _rate 5vsb 3?h0 this selects the weighting of the difference between ta and tb if ta is higher than tb. 3?h1: 1 (ct = 1) 3?h2: 1/2 (ct= 1/2) 3?h3: 1/4 (ct = 1/4) 3?h4: 1/8 (ct = 1/8) otherwise: 0 to access this byte, fan_pr og_sel must set to ?1?. 3 reserved - - reserved 2-0 tfan1_adj_dn _rate r/w 5vsb 3?h0 this selects the weighting of the difference between ta and tb if ta is lower than tb. 3?h1: 1 (ct = 1) 3?h2: 1/2 (ct= 1/2) 3?h3: 1/4 (ct = 1/4) 3?h4: 1/8 (ct = 1/8) otherwise: 0 to access this byte, fan_pr og_sel must set to ?1?.
F81867 dec, 2011 v0.12p 241 fan mode select register ? offset 96h (fan_prog_sel = 0) bit name r/w reset default description 7-6 reserved - - - reserved 5-4 fan3_mode r/w vbat 01 00: auto fan speed control. fan speed will follow different temperature by different rpm defined in 0xc6-0xce. 01: auto fan speed control. fan speed will follow different temperature by different duty cycle defined in 0xc6-0xce. 10: manual mode fan control. user can write expected rpm count to 0xc2-0xc3, and F81867 will adjust duty cycle (pwm fan type) or voltage (linear fan type) to control fan speed automatically. 11: manual mode fan control. user can write expected duty cycle (pwm fan type) or voltage (linear fan type) to 0xc3, and F81867 will output this desired duty or voltage to control fan speed. 3-2 fan2_mode r/w vbat 01 00: auto fan speed control. fan speed will follow different temperature by different rpm defined in 0xb6-0xbe. 01: auto fan speed control. fan speed will follow different temperature by different duty cycle (voltage) defined in 0xb6-0xbe. 10: manual mode fan control. user can write expected rpm count to 0xb2-0xb3, and F81867 will adjust duty cycle (pwm fan type) or voltage (linear fan type) to control fan speed automatically. 11: manual mode fan control, user can write expected duty cycle (pwm fan type) or voltage (linear fan type) to 0xb3, and F81867 will output this desired duty or voltage to control fan speed.
F81867 dec, 2011 v0.12p 242 1-0 fan1_mode r/w vbat 01 00: auto fan speed control. fan speed will follow different temperature by different rpm defined in 0xa6-0xae. 01: auto fan speed control. fan speed will follow different temperature by different duty cycle defined in 0xa6-0xae. 10: manual mode fan control, user can write expected rpm count to 0xa2-0xa3, and F81867 will auto control duty cycle (pwm fan type) or voltage (linea r fan type) to control fan speed automatically. 11: manual mode fan control, user can write expected duty cycle (pwm fan type) or voltage (linear fan type) to 0xa3, and F81867 will output this desired duty or voltage to control fan speed. fan1 adjustment temperature select regi ster ? offset 96h (fan_prog_sel = 1) bit name r/w reset default description 7-3 reserved - - - reserved 2-0 tfan1_adj_sel r/w 5vsb 0h this selects which temperature to be used as ta for fan1 temperature adjustment. 000: peci (cr7eh) 001: t1 (cr72h) 010: t2 (cr74h) 011: t0 (cr70h) 100: ibx/tsi cpu temperature (cr7ah) 101:ibx pch temperature (cr7bh). 110: ibx mch temperature (cr7ch). 111: ibx maximum temperature (cr7dh). to access this register fa n_prog_sel must set to ?1?. faster fan filter control register ? offset 97h bit name r/w reset default description 7-3 reserved - - - reserved. 2 flt_fast3 r/w 5vsb 0 set this bit 1 if fan3 is using a faster fan. 1 flt_fast2 r/w 5vsb 0 set this bit 1 if fan2 is using a faster fan. 0 flt_fast1 r/w 5vsb 0 set this bit 1 if fan1 is using a faster fan.
F81867 dec, 2011 v0.12p 243 auto fan1 and fan2 boundary hystersis select register ? offset 98h bit name r/w reset default description 7-4 fan2_hys r/w 5vsb 4h boundary hysteresis. (0~15 o c) segment will change when the temperature over the boundary temperature and below the ( boundary ? hysteresis). 3-0 fan1_hys r/w 5vsb 4h boundary hysteresis. (0~15 o c) segment will change when the temperature over the boundary temperature and below the ( boundary ? hysteresis). auto fan3 boundary hystersis select register ? offset 99h bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 fan3_hys r/w 5vsb 2h boundary hysteresis. (0~15 o c) segment will change when the temperature over the boundary temperature and below the ( boundary ? hysteresis). fan3 control register ? offset 9ah bit name r/w reset default description 7 reserved - - - reserved. 6 freq_sel_add3 r/w 5vsb 0 this bit and fan3_pwm_freq_sel are used to select fan3 pwm frequency. new_freq_ sel3 = { freq_sel_add3, fan3_pwm_freq_sel} 00: 23.5 khz 01: 11.75 khz 10: 5.875 khz 11: 220 hz 5 freq_sel_add2 r/w 5vsb 0 this bit and fan2_pwm_freq_sel are used to select fan2 pwm frequency. new_freq_ sel2 = { freq_sel_add2, fan2_pwm_freq_sel} 00: 23.5 khz 01: 11.75 khz 10: 5.875 khz 11: 220 hz
F81867 dec, 2011 v0.12p 244 4 freq_sel_add1 r/w 5vsb 0 this bit and fan1_pwm_freq_sel are used to select fan1 pwm frequency. new_freq_ sel1 = { freq_sel_add1, fan1_pwm_freq_sel} 00: 23.5 khz 01: 11.75 khz 10: 5.875 khz 11: 220 hz 3-2 reserved r/w - 0 reserved (keep the value of these two bits ?0?) 1-0 reserved - - - reserved auto fan up speed update rate select register ? offset 9bh fan_prog_sel = 0 bit name r/w reset default description 7-6 reserved - - - reserved. 5-4 fan3_up_rate r/w 5vsb 01 fan3 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 3-2 fan2_up_rate r/w 5vsb 01 fan2 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 1-0 fan1_up_rate r/w 5vsb 01 fan1 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz auto fan down speed update rate select register -- offset 9bh fan_prog_sel = 1 bit name r/w reset default description 7 up_dn_rate_en r/w 5vsb 0 0: fan down rate disable 1: fan down rate enable 6 d irect_load_en r/w 5vsb 0 0: direct load disable 1: direct load enable for manual duty mode
F81867 dec, 2011 v0.12p 245 5-4 fan3_dn_rate r/w 5vsb 01 fan3 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 3-2 fan2_dn_rate r/w 5vsb 01 fan2 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 1-0 fan1_dn_rate r/w 5vsb 01 fan1 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz fan1 and fan2 start up duty-cycle/voltage ? offset 9ch bit name r/w reset default description 7-4 fan2_stop _duty r/w 5vsb 5h when fan start, the fan_ctrl2 will increase duty-cycle from 0 to this (value x 8) directly. and if fan speed is down, the fan_ctrl 2 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). 3-0 fan1_stop _duty r/w 5vsb 5h when fan start, the fan_ctrl 1 w ill increase duty-cycle from 0 to this (value x 8 directly. and if fan speed is down, the fan_ctrl 1 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). fan3 start up duty-cycle/voltage ? offset 9dh bit name r/w reset default description 7-4 reserved - - - reserved. 3-0 fan3_stop_ duty r/w 5vsb 5h when fan start, the fan_ctrl 3 w ill increase duty-cycle from 0 to this (value x 8 directly. and if fan speed is down, the fan_ctrl 3 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4).
F81867 dec, 2011 v0.12p 246 fan programmable duty-cycle/voltage loaded after power-on ? offset 9eh bit name r/w reset default description 7-0 prog_duty_val r/w 5vsb 66h this byte will be immediately loaded as fan duty value after vdd is powered on if it has been programmed before shut down. fan fault time register ? offset 9fh bit name r/w reset default description 7 fan_prog_sel r/w 5vsb 0 set this bit to ?1? will enable accessing registers of other bank. 6 fan_mnt_sel r/w 5vsb 0 set this bit to monitor a slower fan. 5 reserved - - - reserved 4 full_duty_sel r/w 3vcc - 0: the fan duty is 100% and will be loaded immediately after vdd is powered on if cr9e is not been programmed before shut down. (pull down by external resistor) 1: the fan duty is 40% and will be loaded immediately after vdd is powered on if cr9e is not been programmed before shut down. (pull up by internal 47k resistor). this register is power on trap by dtr1#. 3-0 f_fault_time r/w 5vsb ah this register determines the time of fan fault. the condition to cause fan fault event is: when pwm_duty reaches ffh, if the fan speed count can?t reach the fan expect count in time. the unit of this register is 1 second. the default value is 11 seconds. (set to 0 , means 1 seconds. ; set to 1, means 2 seconds. set to 2, means 3 seconds. ?. ) another condition to cause fan fault event is fan stop and the pwm duty is greater than the minimum duty programmed by the register offset 9c-9dh.
F81867 dec, 2011 v0.12p 247 d. fan1 offset a0h~afh address attribute reset default value description a0h ro 3vcc 8?h0f fan1 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read t he fan count correctly, read msb first and followed read the lsb. a1h ro 3vcc 8?hff fan1 count reading (lsb). a2h r/w vbat 8?h00 rpm mode(cr96 bit0=0): fan1 expect speed count val ue (msb), in auto fan mode (cr96 bit1(0) this register is auto updated by hardware. duty mode(cr96 bit0=1): this byte is reserved byte. a3h r/w vbat 8?h01 rpm mode(cr96 bit0=0): fan1 expect speed count value (lsb) or expect pwm duty, in auto fan mode this register is auto updated by hardware and read only. duty mode(cr96 bit0=1): the value programming in this byte is duty value. in auto fan mode (cr96 bit1(0) this register is updated by hardware. ex: 5( 5*100/255 % 255 ( 100% a4h r/w 5vsb 8?h03 fan1 full speed count reading (msb). at the moment of reading this register, the lsb will be latc hed. this will prevent from data updating when reading. to read t he fan count correctly, read msb first and followed read the lsb. a5h r/w 5vsb 8?hff fan1 full speed count reading (lsb). vt1 boundary 1 temperature ? offset a6h bit name r/w reset default description 7-0 bound1tmp1 r/w 5vsb 3ch (60oc) the first boundary temperature for vt1 in temperature mode. when vt1 temperature exceeds this boundary, expected fan1 value will be loaded from segment 1 register (offset aah). when vt1 temperature is under this boundary ? hysteresis, expected fan1 value will be load ed from segment 2 register (offset abh). this byte is a 2?s complement value ranged from -128?c ~ 127?c.
F81867 dec, 2011 v0.12p 248 vt1 boundary 2 temperature ? offset a7 bit name r/w reset default description 7-0 bound2tmp1 r/w 5vsb 32 (50oc) the 2nd boundary temperature for vt1 in temperature mode. when vt1 temperature is exceed this boundary, fan1 expected value will load from segment 2 register (offset abh). when vt1 temperature is below this boundary ? hysteresis, fan1 expected value will load from segment 3 register (offset ach). this byte is a 2?s complement value ranging from -128oc ~ 127oc. vt1 boundary 3 temperature ? offset a8h bit name r/w reset default description 7-0 bound3tmp1 r/w 5vsb 28h (40oc) the 3rd boundary temperature for vt1 in temperature mode. when vt1 temperature is exceed this boundary, fan1 expected value will load from segment 3 register (offset ach). when vt1 temperature is below this boundary ? hysteresis, fan1 expected value will load from segment 4 register (offset adh). this byte is a 2?s complement value ranging from -128oc ~ 127oc. vt1 boundary 4 temperature ? offset a9 bit name r/w reset default description 7-0 bound4tmp1 r/w 5vsb 1eh (30oc) the 4th boundary temperature for vt1 in temperature mode. when vt1 temperature is exceed this boundary, fan1 expected value will load from segment 4 register (offset adh). when vt1 temperature is below this boundary ? hysteresis, fan1 expected value will load from segment 5 register (offset aeh). this byte is a 2?s complement value ranging from -128oc ~ 127oc. fan1 segment 1 speed count ? offset aah bit name r/w reset default description 7 - 0 sec1speed1 r /w 5vsb ffh (100%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. ex: 100%:full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ( (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section.
F81867 dec, 2011 v0.12p 249 fan1 segment 2 speed count ? offset abh bit name r/w reset default description 7-0 sec2speed1 r/w 5vsb d9h (85%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 segment 3 speed count register ? offset ach bit name r/w reset default description 7-0 sec3speed1 r/w 5vsb b2h (70%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 segment 4 speed count register ? offset adh bit name r/w reset default description 7-0 sec4speed1 r/w 5vsb 99h (60%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 segment 5 speed count register ? offset aeh bit name r/w reset default description 7-0 sec5peed1 r/w 5vsb 80h (50%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section.
F81867 dec, 2011 v0.12p 250 fan1 temperature mapping select ? offset afh bit name r/w reset default description 7 fan1_temp _sel_dig r/w 5vsb 0 this bit companies with fan1_temp_sel select the temperature source for controlling fan1. 6 fan1_pwm _freq_sel r/w 5vsb 0 this bit and freq_sel_add1 are used to select fan1 pwm frequency. new_freq_sel1 = { freq_sel_add1, fan1_pwm_freq_sel} 00: 23.5 khz 01: 11.75 khz 10: 5.875 khz 11: 220 hz 5 fan1_up_t_en r/w 5vsb 0 set 1 to force fan1 to full speed if any temperature over its high limit. 4 fan1_ interpolation_ en r/w 5vsb 1 set 1 will enable the interpolat ion of the fan expect table. 3 fan1_jump _high_en r/w 5vsb 1 this register controls the fan1 duty movement when temperature over highest boundary. 0: the fan1 duty will increases with the slope selected by fan1_rate_sel register. 1: the fan1 duty will directly jumps to the value of sec1speed1 register. this bit only activates in duty mode. 2 fan1_jump _low_en r/w 5vsb 1 this register controls the fan1 duty movement when temperature under (highest boundary ? hysteresis). 0: the fan1 duty will decreases with the slope selected by fan1_rate_sel register. 1: the fan1 duty will directly jumps to the value of sec2speed1 register. this bit only activates in duty mode.
F81867 dec, 2011 v0.12p 251 1 - 0 fan1_temp_sel r /w 5vsb 01 this registers company with fan1_temp_sel_dig select the temperature source for controlling fan1. the following value is comprised by {fan1_temp_sel_dig, fan1_temp_sel} 000: fan1 follows peci temperature (cr7eh) 001: fan1 follows temperature 1 (cr72h). 010: fan1 follows temperature 2 (cr74h). 011: fan1 follows temperature 0 (cr70h). 100: fan1 follows ibx/tsi cpu temperature (cr7ah) 101: fan1 follows ibx pch temperature (cr7bh). 110: fan1 follows ibx m ch temperature (cr7ch). 111: fan1 follows ibx maximum temperature (cr7dh). others are reserved. e. fan2 offset b0h~bfh address attribute reset default value description b0h ro 3vcc 8?h0f fan2 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. b1h ro 3vcc 8?hff fan2 count reading (lsb). b2h r/w vbat 8?h00 rpm mode(cr96 bit2=0): fan2 expect speed count val ue (msb), in auto fan mode(cr96 bit3 ? 0) this register is auto updated by hardware. duty mode(cr96 bit2=1): this byte is reserved byte. b3h r/w vbat 8?h01 rpm mode(cr96 bit2=0): fan2 expect speed count value (lsb) or expect pwm duty , in auto fan mode this register is auto updated by hardware and read only. duty mode(cr96 bit2=1): the value programming in this byte is duty value. in auto fan mode(cr96 bit3 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ( 100%
F81867 dec, 2011 v0.12p 252 b4h r/w 5vsb 8?h03 fan2 full speed count reading (msb). at the moment of reading this register, the lsb will be latc hed. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. b5h r/w 5vsb 8?hff fan2 full speed count reading (lsb). vt2 boundary 1 temperature ? offset b6h bit name r/w reset default description 7-0 bound1tmp2 r/w 5vsb 3ch (60oc) the first boundary temperature for vt2 in temperature mode. when vt2 temperature exceeds this boundary, fan2 expect value will load from segmen t 1 register (offset bah). when vt2 temperature is under this boundary ? hysteresis, fan2 expect value will load fr om segment 2 register (offset bah). this byte is a 2?s complement value ranging from -128?c ~ 127?c. vt2 boundary 2 temperature ? offset b7 bit name r/w reset default description 7-0 bound2tmp2 r/w 5vsb 32 (50oc) the 2nd boundary temperature for vt2 in temperature mode. when vt2 temperature is exceed this boundary, fan2 expected value will load from segment 2 register (offset bbh). when vt2 temperature is below this boundary ? hysteresis, fan2 expected value will load from segment 3 register (offset bch). this byte is a 2?s complement value ranging from -128oc ~ 127oc. vt2 boundary 3 temperature ? offset b8h bit name r/w reset default description 7-0 bound3tmp2 r/w 5vsb 28h (40oc) the 3rd boundary temperature for vt2 in temperature mode. when vt2 temperature is exceed this boundary, fan2 expected value will load from segment 3 register (offset bch). when vt2 temperature is below this boundary ? hysteresis, fan2 expected value will load from segment 4 register (offset bdh). this byte is a 2?s complement value ranging from -128oc ~ 127oc.
F81867 dec, 2011 v0.12p 253 vt2 boundary 4 temperature ? offset b9 bit name r/w reset default description 7-0 bound4tmp2 r/w 5vsb 1eh (30oc) the 4th boundary temperature for vt2 in temperature mode. when vt2 temperature is exceed this boundary, fan2 expected value will load from segment 4 register (offset bdh). when vt2 temperature is below this boundary ? hysteresis, fan2 expected value will load from segment 5 register (offset beh). this byte is a 2?s complement value ranging from -128oc ~ 127oc. fan2 segment 1 speed count ? offset bah bit name r/w reset default description 7-0 sec1speed2 r/w 5vsb ffh (100%) the meaning of this register is depending on the fan2_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. ex: 100%:full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ? (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 segment 2 speed count ? offset bbh bit name r/w reset default description 7 - 0 sec2speed2 r /w 5vsb d9h (85%) the meaning of this register is depending on the fan2_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section.
F81867 dec, 2011 v0.12p 254 fan2 segment 3 speed count register ? offset bch bit name r/w reset default description 7 - 0 sec3speed2 r /w 5vsb b2h (70%) the meaning of this register is depending on the fan2_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 segment 4 speed count register ? offset bdh bit name r/w reset default description 7 - 0 sec4speed2 r /w 5vsb 99h (60%) the meaning of this register is depending on the fan2_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 segment 5 speed count register ? offset beh bit name r/w reset default description 7 - 0 sec5peed2 r /w 5vsb 80h (50%) the meaning of this register is depending on the fan2_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 temperature mapping select ? offset bfh bit name r/w reset default description 7 fan2_temp_ sel_dig r/w 5vsb 0 this bit companies with fan2_temp_sel to select the temperature source for controlling fan2. 6 fan2_pwm_ freq_sel r/w 5vsb 0 this bit and freq_sel_add2 are used to select fan2 pwm frequency. new_freq_sel2 = { freq_sel_add2, fan2_pwm_freq_sel} 00: 23.5 khz 01: 11.75 khz 10: 5.875 khz 11: 220 hz 5 fan2_up_t_en r /w 5vsb 0 set 1 to force fan2 to full speed if any temperature over its high limit.
F81867 dec, 2011 v0.12p 255 4 fan2_ interpolation_en r/w 5vsb 1 set 1 will enable the interpolat ion of the fan expect table. 3 fan2_jump_ high_en r/w 5vsb 1 this register controls the fan2 duty movement when temperature over highest boundary. 0: the fan2 duty will increases with the slope selected by fan2_rate_sel register. 1: the fan2 duty will directly jumps to the value of sec1speed2 register. this bit only activates in duty mode. 2 fan2_jump_ low_en r/w 5vsb 1 this register controls the fan2 duty movement when temperature under (highest boundary ? hysteresis). 0: the fan2 duty will decreases with the slope selected by fan2_rate_sel register. 1: the fan2 duty will directly jumps to the value of sec2speed2 register. this bit only activates in duty mode. 1 - 0 fan2_temp_sel r /w 5vsb 10 this registers companying with fan2_temp_sel_dig select the temperature source for controlling fan2. the following value is comprised by {fan2_temp_sel_dig, fan2_temp_sel} 000: fan2 follows peci temperature (cr7eh) 001: fan2 follows temperature 1 (cr72h). 010: fan2 follows temperature 2 (cr74h). 011: fan2 follows temperature 0 (cr70h). 100: fan2 follows ibex/tsi cpu temperature (cr7ah) 101: fan2 follows ibex pch temperature (cr7bh). 110: fan2 follows ibex m ch temperature (cr7ch). 111: fan2 follows ibex maxi mum temperature (cr7dh). otherwise: reserved. f. fan3 offset c0h- cfh address attribute reset default value description c0h ro 3vcc 8?h0f fan3 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. c1h ro 3vcc 8?hff fan3 count reading (lsb).
F81867 dec, 2011 v0.12p 256 c2h r/w vbat 8?h00 rpm mode(cr96 bit4=0): fan3 expect speed count val ue (msb), in auto fan mode(cr96 bit5 ? 0) this register is auto updated by hardware. duty mode(cr96 bit4=1): this byte is reserved byte. c3h r/w vbat 8?h01 rpm mode(cr96 bit4=0): fan3 expect speed count value (lsb) or expect pwm duty , in auto fan mode this register is auto updated by hardware and read only. duty mode(cr96 bit4=1): the value programming in this byte is duty value. in auto fan mode(cr96 bit5 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% c4h r/w 5vsb 8?h03 fan3 full speed count reading (msb). at the moment of reading this register, the lsb will be latc hed. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. c5h r/w 5vsb 8?hff fan3 full speed count reading (lsb). vt3 boundary 1 temperature ? offset c6h bit name r/w reset default description 7-0 bound1tmp3 r/w 5vsb 3ch (60 o c) the first boundary temperature for vt3 in temperature mode. when vt3 temperature exceeds this boundary, fan3 expect value will load from segment 1 register (offset ca)h. when vt3 temperature is under this boundary ? hysteresis, fan3 expect value will load from segment 2 register (offset cah). this byte is a 2?s complement value ranging from -128?c ~ 127?c. vt3 boundary 2 temperature ? offset c7 bit name r/w reset default description 7-0 bound2tmp3 r/w 5vsb 32 (50 o c) the 2nd boundary temperature for vt3 in temperature mode. when vt3 temperature is exceed this boundary, fan3 expected value will load from segment 2 register (offset cbh). when vt3 temperature is below this boundary ? hysteresis, fan3 expected value will load from segment 3 register (offset cch). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c.
F81867 dec, 2011 v0.12p 257 vt3 boundary 3 temperature ? offset c8h bit name r/w reset default description 7-0 bound3tmp3 r/w 5vsb 28h (40 o c) the 3rd boundary temperature for vt3 in temperature mode. when vt3 temperature is exceed this boundary, fan3 expected value will load from segment 3 register (offset cch). when vt3 temperature is below this boundary ? hysteresis, fan3 expected value will load from segment 4 register (offset cdh). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. vt3 boundary 4 temperature ? offset c9h bit name r/w reset default description 7-0 bound4tmp3 r/w 5vsb 1eh (30 o c) the 4th boundary temperature for vt3 in temperature mode. when vt3 temperature is exceed this boundary, fan3 expected value will load from segment 4 register (offset cdh). when vt3 temperature is below this boundary ? hysteresis, fan3 expected value will load from segment 5 register (offset ceh). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. fan3 segment 1 speed count ? offset cah bit name r/w reset default description 7 - 0 sec1speed3 r /w 5vsb ffh (100%) the meaning of this register is depending on the fan3_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. ex: 100%:full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ( (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section.
F81867 dec, 2011 v0.12p 258 fan3 segment 2 speed count ? offset cbh bit name r/w reset default description 7-0 sec2speed3 r/w 5vsb d9h (85%) the meaning of this register is depending on the fan3_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan3 segment 3 speed co unt ? offset cch bit name r/w reset default description 7-0 sec3speed3 r/w 5vsb b2h (70%) the meaning of this register is depending on the fan3_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan3 segment 4 speed co unt ? offset cdh bit name r/w reset default description 7-0 sec4speed3 r/w 5vsb 99h (60%) the meaning of this register is depending on the fan3_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan3 segment 5 speed co unt ? offset ceh bit name r/w reset default description 7-0 sec5speed3 r/w 5vsb 80h (50%) the meaning of this register is depending on the fan3_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan3 temperature mapping select ? offset cfh bit name r/w reset default description 7 fan3_temp_ sel_dig r/w 5vsb 0 this bit companies with fan3_temp_sel select the temperature source for controlling fan3.
F81867 dec, 2011 v0.12p 259 6 fan3_pwm_ freq_sel r/w 5vsb 0 this bit and freq_sel_add3 are used to select fan3 pwm frequency. new_freq_sel3 = { freq_sel_add3, fan3_pwm_freq_sel} 00: 23.5 khz 01: 11.75 khz 10: 5.875 khz 11: 220 hz 5 fan3_up_t_en r /w 5vsb 0 set 1 to force fan3 to full speed if any temperature over its high limit. 4 fan3_ interpolation_en r/w 5vsb 1 set 1 will enable the interpolat ion of the fan expect table. 3 fan3_jump_ high_en r/w 5vsb 1 this register controls the fan3 duty movement when temperature over highest boundary. 0: the fan3 duty will increases with the slope selected by fan3_rate_sel register. 1: the fan3 duty will directly jumps to the value of sec1speed3 register. this bit only activates in duty mode. 2 fan3_jump_ low_en r/w 5vsb 1 this register controls the fan3 duty movement when temperature under (highest boundary ? hysteresis). 0: the fan3 duty will decreases with the slope selected by fan3_rate_sel register. 1: the fan3 duty will directly jumps to the value of sec2speed3 register. this bit only activates in duty mode. 1 - 0 fan3_temp_sel r /w 5vsb 11 this registers companying with fan3_temp_sel_dig select the temperature source for controlling fan3. the following value is comprised by {fan3_temp_sel_dig, fan3_temp_sel} 000: fan3 follows peci temperature (cr7eh) 001: fan3 follows temperature 1 (cr72h). 010: fan3 follows temperature 2 (cr74h). 011: fan3 follows temperature 0 (cr70h). 100: fan3 follows ibex/tsi cpu temperature (cr7ah) 101: fan3 follows ibex pch temperature (cr7bh). 110: fan3 follows ibex m ch temperature (cr7ch). 111: fan3 follows ibex maxi mum temperature (cr7dh). otherwise: reserved.
F81867 dec, 2011 v0.12p 260 7.20.9 gpio c side register (base address 0x2100, 256 bytes) gpio0 output enable register ? offset f0h. bit name r/w reset default description 7 gpio07_oe r/w 5vsb 0 0: gpio07 is in input mode. 1: gpio07 is in output mode. 6 gpio06_oe r/w 5vsb 0 0: gpio06 is in input mode. 1: gpio06 is in output mode. 5 gpio05_oe r/w 5vsb 0 0: gpio05 is in input mode. 1: gpio05 is in output mode. 4 gpio04_oe r/w 5vsb 0 0: gpio04 is in input mode. 1: gpio04 is in output mode. 3 gpio03_oe r/w 5vsb 0 0: gpio03 is in input mode. 1: gpio03 is in output mode. 2 gpio02_oe r/w 5vsb 0 0: gpio02 is in input mode. 1: gpio02 is in output mode. 1 gpio01_oe r/w 5vsb 0 0: gpio01 is in input mode. 1: gpio01 is in output mode. 0 gpio00_oe r/w 5vsb 0 0: gpio00 is in input mode. 1: gpio00 is in output mode. gpio0 output data register ? offset f1h bit name r/w reset default description 7 gpio07_val r/w 5vsb 0 gpio07 supports pulse mode. when pulse mode is selected, write ?1? to this bit will assert a pulse from gpio07. auto clear when pulse is finished. when level mode is selected, write 0/1 to this bit will set the level of gpio07. 0: outputs 0 when in output mode. 1: outputs1 when in output mode. gpio 07 will be tri-state if gpio07_drv is clear to ?0?. 6 gpio06_val r/w 5vsb 0 gpio06 supports pulse mode. when pulse mode is selected, write ?1? to this bit will assert a pulse from gpio06. auto clear when pulse is finished. when level mode is selected, write 0/1 to this bit will set the level of gpio06. 0: outputs 0 when in output mode. 1: outputs1 when in output mode. gpio 06 will be tri-state if gpio06_drv is clear to ?0?. 5 gpio05_val r/w 5vsb 0 gpio05 supports pulse mode. when pulse mode is selected, write ?1? to this bit will assert a pulse from gpio05. auto clear when pulse is finished. when level mode is selected, write 0/1 to this bit will set the level of gpio05. 0: outputs 0 when in output mode. 1: outputs1 when in output mode. gpio 05 will be tri-state if gpio05_drv is clear to ?0?.
F81867 dec, 2011 v0.12p 261 4 gpio04_val r/w 5vsb 0 gpio04 supports pulse mode. when pulse mode is selected, write ?1? to this bit will assert a pulse from gpio04. auto clear when pulse is finished. when level mode is selected, write 0/1 to this bit will set the level of gpio04. 0: outputs 0 when in output mode. 1: outputs1 when in output mode. gpio 04 will be tri-state if gpio04_drv is clear to ?0?.1: gpio04 outputs 1 when in output mode. 3 gpio03_val r/w 5vsb 1 0: gpio03 outputs 0 when in output mode. 1: gpio03 outputs 1 when in output mode. 2 gpio02_val r/w 5vsb 1 0: gpio02 outputs 0 when in output mode. 1: gpio02 outputs 1 when in output mode. 1 gpio01_val r/w 5vsb 1 0: gpio01 outputs 0 when in output mode. 1: gpio01 outputs 1 when in output mode. 0 gpio00_val r/w 5vsb 1 0: gpio00 outputs 0 when in output mode. 1: gpio00 outputs 1 when in output mode. gpio0 pin status register ? offset f2h bit name r/w reset default description 7 gpio07_in r - - the pin status of gpio07/rts5#. 6 gpio06_in r - - the pin status of gpio06/sin5. 5 gpio05_in r - - the pin status of gpio05/sout5. 4 gpio04_in r - - the pin status of slp_sus#/gpio04. 3 gpio03_in r - - the pin status of sus_ack#/gpio03/spi_mosi. 2 gpio02_in r - - the pin status of sus_warn#/gpio02/spi_miso. 1 gpio01_in r - - the pin status of erp_ctrl1#/gpio01/spi_cs#. 0 gpio00_in r - - the pin status of erp_ctrl0#/gpio00/spi_clk. gpio0 drive enable register ? offset f3h bit name r/w reset default description 7 gpio07_drv_en r/w 5vsb 0 0: gpio07 is open drain in output mode. 1: gpio07 is push pull in output mode. 6 gpio06_drv_en r/w 5vsb 0 0: gpio06 is open drain in output mode. 1: gpio06 is push pull in output mode. 5 gpio05_drv_en r/w 5vsb 0 0: gpio05 is open drain in output mode. 1: gpio05 is push pull in output mode. 4 gpio04_drv_en r/w 5vsb 0 0: gpio04 is open drain in output mode. 1: gpio04 is push pull in output mode. 3 gpio03_drv_en r/w 5vsb 0 0: gpio03 is open drain in output mode. 1: gpio03 is push pull in output mode. 2 gpio02_drv_en r/w 5vsb 0 0: gpio02 is open drain in output mode. 1: gpio02 is push pull in output mode. 1 gpio01_drv_en r/w 5vsb 0 0: gpio01 is open drain in output mode. 1: gpio01 is push pull in output mode. 0 gpio00_drv_en r/w 5vsb 0 0: gpio00 is open drain in output mode. 1: gpio00 is push pull in output mode.
F81867 dec, 2011 v0.12p 262 gpio0 mode register ? offset f5h bit name r/w reset default description 7-6 gpio07_mode r/w 5vsb 0 the output mode of gpio07. 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. 5-4 gpio06_mode r/w 5vsb 0 the output mode of gpio06. 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. 3-2 gpio05_mode r/w 5vsb 0 the output mode of gpio05. 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. 1-0 gpio04_mode r/w 5vsb 0 the output mode of gpio04. 00: level mode. 01: inverted level mode. 10: high pulse mode. 11: low pulse mode. gpio0 pulse select register ? offset f7h bit name r/w reset default description 7-6 gpio07_pw_sel r/w 5vsb 0 the pulse width of gpio07 in pulse output mode. 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. 5-4 gpio06_pw_sel r/w 5vsb 0 the pulse width of gpio06 in pulse output mode. 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. 3-2 gpio05_pw_sel r/w 5vsb 0 the pulse width of gpio05 in pulse output mode. 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. 1-0 gpio04_pw_sel r/w 5vsb 0 the pulse width of gpio04 in pulse output mode. 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms.
F81867 dec, 2011 v0.12p 263 gpio0 smi enable register ? offset f8h bit name r/w reset default description 7 gpio07_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio07_smi_st is set. 6 gpio06_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio06_smi_st is set. 5 gpio05_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio05_smi_st is set. 4 gpio04_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio04_smi_st is set. 3 gpio03_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio03_smi_st is set. 2 gpio02_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio02_smi_st is set. 1 gpio01_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio01_smi_st is set. 0 gpio00_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio00_smi_st is set. gpio0 smi status register ? offset f9h bit name r/w reset default description 7 gpio07_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio07 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 6 gpio06_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio06 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 5 gpio05_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio05 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 4 gpio04_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio04 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 3 gpio03_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio03 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 2 gpio02_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio02 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 1 gpio01_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio01 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 0 gpio00_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio00 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status.
F81867 dec, 2011 v0.12p 264 gpio1 output enable register ? offset e0h bit name r/w reset default description 7 gpio17_oe r/w 5vsb 0 0: gpio17 is in input mode. 1: gpio17 is in output mode. 6 gpio16_oe r/w 5vsb 0 0: gpio16 is in input mode. 1: gpio16 is in output mode. 5 gpio15_oe r/w 5vsb 0 0: gpio15 is in input mode. 1: gpio15 is in output mode. 4 gpio14_oe r/w 5vsb 0 0: gpio14 is in input mode. 1: gpio14 is in output mode. 3 gpio13_oe r/w 5vsb 0 0: gpio13 is in input mode. 1: gpio13 is in output mode. 2 gpio12_oe r/w 5vsb 0 0: gpio12 is in input mode. 1: gpio12 is in output mode. 1 gpio11_oe r/w 5vsb 0 0: gpio11 is in input mode. 1: gpio11 is in output mode. 0 gpio10_oe r/w 5vsb 0 0: gpio10 is in input mode. 1: gpio10 is in output mode. gpio1 output data register ? offset e1h bit name r/w reset default description 7 gpio17_val r/w 5vsb 1 0: gpio17 outputs 0 when in output mode. 1: gpio17 outputs1 when in output mode. 6 gpio16_val r/w 5vsb 1 0: gpio16 outputs 0 when in output mode. 1: gpio16 outputs1 when in output mode. 5 gpio15_val r/w 5vsb 1 0: gpio15 outputs 0 when in output mode. 1: gpio15 outputs 1 when in output mode. 4 gpio14_val r/w 5vsb 1 0: gpio14 outputs 0 when in output mode. 1: gpio14 outputs 1 when in output mode. 3 gpio13_val r/w 5vsb 1 0: gpio13 outputs 0 when in output mode. 1: gpio13 outputs 1 when in output mode. 2 gpio12_val r/w 5vsb 1 0: gpio12 outputs 0 when in output mode. 1: gpio12 outputs 1 when in output mode. 1 gpio11_val r/w 5vsb 1 0: gpio11 outputs 0 when in output mode. 1: gpio11 outputs 1 when in output mode. 0 gpio10_val r/w 5vsb 1 0: gpio10 outputs 0 when in output mode. 1: gpio10 outputs 1 when in output mode. gpio1 pin status register ? offset e2h bit name r/w reset default description 7 gpio17_in r - - the pin status of peci/gpio17. 6 gpio16_in r - - the pin status of beep/gpio16/sda/cirrx#. 5 gpio15_in r - - the pin status of wdtrst#/gpio15. 4 gpio14_in r - - the pin status of gpio14/at_atx_trap. 3 gpio13_in r - - the pin status of sda/gpio13/irrx.
F81867 dec, 2011 v0.12p 265 2 gpio12_in r - - the pin status of scl/gpio12/irtx 1 gpio11_in r - - the pin status of gpio11/led_vcc. 0 gpio10_in r - - the pin status of gpio10/led_vsb. gpio1 drive enable register ? offset e3h bit name r/w reset default description 7 gpio17_drv_en r/w 5vsb 0 0: gpio17 is open drain in output mode. 1: gpio17 is push pull in output mode. 6 gpio16_drv_en r/w 5vsb 0 0: gpio16 is open drain in output mode. 1: gpio16 is push pull in output mode. 5 gpio15_drv_en r/w 5vsb 0 0: gpio15 is open drain in output mode. 1: gpio15 is push pull in output mode. 4 gpio14_drv_en r/w 5vsb 0 0: gpio14 is open drain in output mode. 1: gpio14 is push pull in output mode. 3 gpio13_drv_en r/w 5vsb 0 0: gpio13 is open drain in output mode. 1: gpio13 is push pull in output mode. 2 gpio12_drv_en r/w 5vsb 0 0: gpio12 is open drain in output mode. 1: gpio12 is push pull in output mode. 1 gpio11_drv_en r/w vbat 0 0: gpio11 is open drain in output mode. 1: gpio11 is push pull in output mode. this bit is powered by vbat. 0 gpio10_drv_en r/w vbat 0 0: gpio10 is open drain in output mode. 1: gpio10 is push pull in output mode. this bit is powered by vbat. gpio1 smi enable register ? offset e8h bit name r/w reset default description 7 gpio17_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio17_smi_st is set. 6 gpio16_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio16_smi_st is set. 5 gpio15_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio15_smi_st is set. 4 gpio14_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio14_smi_st is set. 3 gpio13_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio13_smi_st is set. 2 gpio12_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio12_smi_st is set. 1 gpio11_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio11_smi_st is set. 0 gpio10_smi_en r/w 5vsb 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio10_smi_st is set.
F81867 dec, 2011 v0.12p 266 gpio1 smi status register ? offset e9h bit name r/w reset default description 7 gpio17_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio17 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 6 gpio16_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio16 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 5 gpio15_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio15 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 4 gpio14_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio14 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 3 gpio13_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio13 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 2 gpio12_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio12 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 1 gpio11_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio11 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 0 gpio10_smi_st r/w 5vsb 0 0: no smi event. 1: a smi event will set if gpio10 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. gpio2 output enable register ? offset d0h bit name r/w reset default description 7 gpio27_oe r/w 5vsb 0 0: gpio27 is in input mode. 1: gpio27 is in output mode. 6 gpio26_oe r/w 5vsb 0 0: gpio26 is in input mode. 1: gpio25 is in output mode. 5 gpio25_oe r/w 5vsb 0 0: gpio25 is in input mode. 1: gpio25 is in output mode. 4 gpio24_oe r/w 5vsb 0 0: gpio24 is in input mode. 1: gpio24 is in output mode. 3 gpio23_oe r/w 5vsb 0 0: gpio23 is in input mode. 1: gpio23 is in output mode. 2 gpio22_oe r/w 5vsb 0 0: gpio22 is in input mode. 1: gpio22 is in output mode. 1 gpio21_oe r/w 5vsb 0 0: gpio21 is in input mode. 1: gpio21 is in output mode. 0 gpio20_oe r/w 5vsb 0 0: gpio20 is in input mode. 1: gpio20 is in output mode.
F81867 dec, 2011 v0.12p 267 gpio2 output data register ? offset d1h bit name r/w reset default description 7 gpio27_val r/w 5vsb 1 0: gpio27 outputs 0 when in output mode. 1: gpio27 outputs 1 when in output mode. 6 gpio26_val r/w 5vsb 1 0: gpio26 outputs 0 when in output mode. 1: gpio26 outputs 1 when in output mode. 5 gpio25_val r/w 5vsb 1 0: gpio25 outputs 0 when in output mode. 1: gpio25 outputs 1 when in output mode. 4 gpio24_val r/w 5vsb 1 0: gpio25 outputs 0 when in output mode. 1: gpio25 outputs 1 when in output mode. 3 gpio23_val r/w 5vsb 1 0: gpio23 outputs 0 when in output mode. 1: gpio23 outputs 1 when in output mode. 2 gpio22_val r/w 5vsb 1 0: gpio22 outputs 0 when in output mode. 1: gpio22 outputs 1 when in output mode. 1 gpio21_val r/w 5vsb 1 0: gpio21 outputs 0 when in output mode. 1: gpio21 outputs 1 when in output mode. 0 gpio20_val r/w 5vsb 1 0: gpio20 outputs 0 when in output mode. 1: gpio20 outputs 1 when in output mode. gpio2 pin status register ? offset d2h bit name r/w reset default description 7 gpio27_in r - - the pin status of rsmrst#/gpio27. 6 gpio26_in r - - the pin status of pwrok/gpio26. 5 gpio25_in r - - the pin status of pson#/gpio25. 4 gpio24_in r - - the pin status of s3#/gpio24. 3 gpio23_in r - - the pin status of pwsout#/gpio23. 2 gpio22_in r - - the pin status of pwsin#/gpio22. 1 gpio21_in r - - the pin status of atxpg/gpio21. 0 gpio20_in r - - the pin status of alert#/gpio20/scl/cirrx#. gpio2 drive enable register ? offset d3h bit name r/w reset default description 7-6 reserved - 5vsb - reserved. 5 gpio25_drv_en r/w 5vsb 0 0: gpio25 is open drain in output mode. 1: gpio25 is push pull in output mode. 4 gpio24_drv_en r/w 5vsb 0 0: gpio25 is open drain in output mode. 1: gpio25 is push pull in output mode. 3 gpio23_drv_en r/w 5vsb 0 0: gpio23 is open drain in output mode. 1: gpio23 is push pull in output mode. 2 gpio22_drv_en r/w 5vsb 0 0: gpio22 is open drain in output mode. 1: gpio22 is push pull in output mode. 1 gpio21_drv_en r/w 5vsb 0 0: gpio21 is open drain in output mode. 1: gpio21 is push pull in output mode. 0 gpio20_drv_en r/w 5vsb 0 0: gpio20 is open drain in output mode. 1: gpio20 is push pull in output mode.
F81867 dec, 2011 v0.12p 268 5vsb gpio3 output enable register ? offset c0h bit name r/w reset default description 7 gpio37_oe r/w lreset# 0 0: gpio37 is in input mode. 1: gpio37 is in output mode. 6 gpio36_oe r/w lreset# 0 0: gpio36 is in input mode. 1: gpio35 is in output mode. 5 gpio35_oe r/w lreset# 0 0: gpio35 is in input mode. 1: gpio35 is in output mode. 4 gpio34_oe r/w lreset# 0 0: gpio34 is in input mode. 1: gpio34 is in output mode. 3 gpio33_oe r/w lreset# 0 0: gpio33 is in input mode. 1: gpio33 is in output mode. 2 gpio32_oe r/w lreset# 0 0: gpio32 is in input mode. 1: gpio32 is in output mode. 1 gpio31_oe r/w lreset# 0 0: gpio31 is in input mode. 1: gpio31 is in output mode. 0 gpio30_oe r/w lreset# 0 0: gpio30 is in input mode. 1: gpio30 is in output mode. gpio3 output data register ? offset c1h bit name r/w reset default description 7 gpio37_val r/w lreset# 1 0: gpio37 outputs 0 when in output mode. 1: gpio37 outputs 1 when in output mode. 6 gpio36_val r/w lreset# 1 0: gpio36 outputs 0 when in output mode. 1: gpio36 outputs 1 when in output mode. 5 gpio35_val r/w lreset# 1 0: gpio35 outputs 0 when in output mode. 1: gpio35 outputs 1 when in output mode. 4 gpio34_val r/w lreset# 1 0: gpio34 outputs 0 when in output mode. 1: gpio34 outputs 1 when in output mode. 3 gpio33_val r/w lreset# 1 0: gpio33 outputs 0 when in output mode. 1: gpio33 outputs 1 when in output mode. 2 gpio32_val r/w lreset# 1 0: gpio32 outputs 0 when in output mode. 1: gpio32 outputs 1 when in output mode. 1 gpio31_val r/w lreset# 1 0: gpio31 outputs 0 when in output mode. 1: gpio31 outputs 1 when in output mode. 0 gpio30_val r/w lreset# 1 0: gpio30 outputs 0 when in output mode. 1: gpio30 outputs 1 when in output mode. gpio3 pin status register ? offset c2h bit name r/w reset default description 7 gpio37_in r - - the pin status of sin3/gpio37. 6 gpio36_in r - - the pin status of sout3/gpio36. 5 gpio35_in r - - the pin status of dsr3#/gpio35.
F81867 dec, 2011 v0.12p 269 4 gpio34_in r - - the pin status of rts3#/gpio34. 3 gpio33_in r - - the pin status of dtr3#/gpio33. 2 gpio32_in r - - the pin status of cts3#/gpio32. 1 gpio31_in r - - the pin status of ri3#/gpio31. 0 gpio30_in r - - the pin status of dcd3#/gpio30. gpio3 drive enable register ? offset c3h bit name r/w reset default description 7 gpio37_drv_en r/w lreset# 0 0: gpio37 is open drain in output mode. 1: gpio37 is push pull in output mode. 6 gpio36_drv_en r/w lreset# 0 0: gpio36 is open drain in output mode. 1: gpio36 is push pull in output mode. 5 gpio35_drv_en r/w lreset# 0 0: gpio35 is open drain in output mode. 1: gpio35 is push pull in output mode. 4 gpio34_drv_en r/w lreset# 0 0: gpio34 is open drain in output mode. 1: gpio34 is push pull in output mode. 3 gpio33_drv_en r/w lreset# 0 0: gpio33 is open drain in output mode. 1: gpio33 is push pull in output mode. 2 gpio32_drv_en r/w lreset# 0 0: gpio32 is open drain in output mode. 1: gpio32 is push pull in output mode. 1 gpio31_drv_en r/w lreset# 0 0: gpio31 is open drain in output mode. 1: gpio31 is push pull in output mode. 0 gpio30_drv_en r/w lreset# 0 0: gpio30 is open drain in output mode. 1: gpio30 is push pull in output mode. gpio4 output enable register ? offset b0h bit name r/w reset default description 7 gpio47_oe r/w lreset# 0 0: gpio47 is in input mode. 1: gpio47 is in output mode. 6 gpio46_oe r/w lreset# 0 0: gpio46 is in input mode. 1: gpio45 is in output mode. 5 gpio45_oe r/w lreset# 0 0: gpio45 is in input mode. 1: gpio45 is in output mode. 4 gpio44_oe r/w lreset# 0 0: gpio44 is in input mode. 1: gpio44 is in output mode. 3 gpio43_oe r/w lreset# 0 0: gpio43 is in input mode. 1: gpio43 is in output mode. 2 gpio42_oe r/w lreset# 0 0: gpio42 is in input mode. 1: gpio42 is in output mode. 1 gpio41_oe r/w lreset# 0 0: gpio41 is in input mode. 1: gpio41 is in output mode. 0 gpio40_oe r/w lreset# 0 0: gpio40 is in input mode. 1: gpio40 is in output mode.
F81867 dec, 2011 v0.12p 270 gpio4 output data register ? offset b1h bit name r/w reset default description 7 gpio47_val r/w lreset# 1 0: gpio47 outputs 0 when in output mode. 1: gpio47 outputs 1 when in output mode. 6 gpio46_val r/w lreset# 1 0: gpio46 outputs 0 when in output mode. 1: gpio46 outputs 1 when in output mode. 5 gpio45_val r/w lreset# 1 0: gpio45 outputs 0 when in output mode. 1: gpio45 outputs 1 when in output mode. 4 gpio44_val r/w lreset# 1 0: gpio44 outputs 0 when in output mode. 1: gpio44 outputs 1 when in output mode. 3 gpio43_val r/w lreset# 1 0: gpio43 outputs 0 when in output mode. 1: gpio43 outputs 1 when in output mode. 2 gpio42_val r/w lreset# 1 0: gpio42 outputs 0 when in output mode. 1: gpio42 outputs 1 when in output mode. 1 gpio41_val r/w lreset# 1 0: gpio41 outputs 0 when in output mode. 1: gpio41 outputs 1 when in output mode. 0 gpio40_val r/w lreset# 1 0: gpio40 outputs 0 when in output mode. 1: gpio40 outputs 1 when in output mode. gpio4 pin status register ? offset b2h bit name r/w reset default description 7 gpio47_in r - - the pin status of sin4/gpio47. 6 gpio46_in r - - the pin status of sout4/gpio46. 5 gpio45_in r - - the pin status of dsr4#/gpio45. 4 gpio44_in r - - the pin status of rts4#/gpio44. 3 gpio43_in r - - the pin status of dtr4#/gpio43. 2 gpio42_in r - - the pin status of cts4#/gpio42. 1 gpio41_in r - - the pin status of ri4#/gpio41. 0 gpio40_in r - - the pin status of dcd4#/gpio40. gpio4 drive enable register ? offset b3h bit name r/w reset default description 7 gpio47_drv_en r/w lreset# 0 0: gpio47 is open drain in output mode. 1: gpio47 is push pull in output mode. 6 gpio46_drv_en r/w lreset# 0 0: gpio46 is open drain in output mode. 1: gpio46 is push pull in output mode. 5 gpio45_drv_en r/w lreset# 0 0: gpio45 is open drain in output mode. 1: gpio45 is push pull in output mode. 4 gpio44_drv_en r/w lreset# 0 0: gpio44 is open drain in output mode. 1: gpio44 is push pull in output mode. 3 gpio43_drv_en r/w lreset# 0 0: gpio43 is open drain in output mode. 1: gpio43 is push pull in output mode. 2 gpio42_drv_en r/w lreset# 0 0: gpio42 is open drain in output mode. 1: gpio42 is push pull in output mode.
F81867 dec, 2011 v0.12p 271 1 gpio41_drv_en r/w lreset# 0 0: gpio41 is open drain in output mode. 1: gpio41 is push pull in output mode. 0 gpio40_drv_en r/w lreset# 0 0: gpio40 is open drain in output mode. 1: gpio40 is push pull in output mode. gpio5 output enable register ? offset a0h bit name r/w reset default description 7 gpio57_oe r/w lreset# 0 0: gpio57 is in input mode. 1: gpio57 is in output mode. 6 gpio56_oe r/w lreset# 0 0: gpio56 is in input mode. 1: gpio56 is in output mode. 5 gpio55_oe r/w lreset# 0 0: gpio55 is in input mode. 1: gpio55 is in output mode. 4 gpio54_oe r/w lreset# 0 0: gpio54 is in input mode. 1: gpio54 is in output mode. 3 gpio53_oe r/w lreset# 0 0: gpio53 is in input mode. 1: gpio53 is in output mode. 2 gpio52_oe r/w lreset# 0 0: gpio52 is in input mode. 1: gpio52 is in output mode. 1 gpio51_oe r/w lreset# 0 0: gpio51 is in input mode. 1: gpio51 is in output mode. 0 gpio50_oe r/w lreset# 0 0: gpio50 is in input mode. 1: gpio50 is in output mode. gpio5 output data register ? offset a1h bit name r/w reset default description 7 gpio57_val r/w lreset# 1 0: gpio57 outputs 0 when in output mode. 1: gpio57 outputs 1 when in output mode. 6 gpio56_val r/w lreset# 1 0: gpio56 outputs 0 when in output mode. 1: gpio56 outputs 1 when in output mode. 5 gpio55_val r/w lreset# 1 0: gpio55 outputs 0 when in output mode. 1: gpio55 outputs 1 when in output mode. 4 gpio54_val r/w lreset# 1 0: gpio54 outputs 0 when in output mode. 1: gpio54 outputs 1 when in output mode. 3 gpio53_val r/w lreset# 1 0: gpio53 outputs 0 when in output mode. 1: gpio53 outputs 1 when in output mode. 2 gpio52_val r/w lreset# 1 0: gpio52 outputs 0 when in output mode. 1: gpio52 outputs 1 when in output mode. 1 gpio51_val r/w lreset# 1 0: gpio51 outputs 0 when in output mode. 1: gpio51 outputs 1 when in output mode. 0 gpio50_val r/w lreset# 1 0: gpio50 outputs 0 when in output mode. 1: gpio50 outputs 1 when in output mode.
F81867 dec, 2011 v0.12p 272 gpio5 pin status register ? offset a2h bit name r/w reset default description 4 gpio57_in r - - the pin status of gpio57/wgate#/dsr6#/t2ex. 4 gpio56_in r - - the pin status of gpio56/hdsel#/dtr6#/t2. 4 gpio55_in r - - the pin status of gpio55/step#/cts6#/p35. 4 gpio54_in r - - the pin status of gpio54/dir#/ri6#/p34. 3 gpio53_in r - - the pin status of gpio53/wdata#/dcd6#/p33. 2 gpio52_in r - - the pin status of gp io52/drva#/sout6/p32. 1 gpio51_in r - - the pin status of gpio51/moa#/sin6/p31. 0 gpio50_in r - - the pin status of gp io50/densel#/rts6#/p30. gpio5 drive enable register ? offset a3h bit name r/w reset default description 7 gpio57_drv_en r/w lreset# 0 0: gpio57 is open drain in output mode. 1: gpio57 is push pull in output mode. 6 gpio56_drv_en r/w lreset# 0 0: gpio56 is open drain in output mode. 1: gpio56 is push pull in output mode. 5 gpio55_drv_en r/w lreset# 0 0: gpio55 is open drain in output mode. 1: gpio55 is push pull in output mode. 4 gpio54_drv_en r/w lreset# 0 0: gpio54 is open drain in output mode. 1: gpio54 is push pull in output mode. 3 gpio53_drv_en r/w lreset# 0 0: gpio53 is open drain in output mode. 1: gpio53 is push pull in output mode. 2 gpio52_drv_en r/w lreset# 0 0: gpio52 is open drain in output mode. 1: gpio52 is push pull in output mode. 1 gpio51_drv_en r/w lreset# 0 0: gpio51 is open drain in output mode. 1: gpio51 is push pull in output mode. 0 gpio50_drv_en r/w lreset# 0 0: gpio50 is open drain in output mode. 1: gpio50 is push pull in output mode. gpio5 smi enable register ? offset a8h bit name r/w reset default description 7 gpio57_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio57_smi_st is set. 6 gpio56_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio56_smi_st is set. 5 gpio55_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio55_smi_st is set. 4 gpio54_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio54_smi_st is set. 3 gpio53_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio53_smi_st is set. 2 gpio52_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio52_smi_st is set.
F81867 dec, 2011 v0.12p 273 1 gpio51_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio51_smi_st is set. 0 gpio50_smi_en r/w lreset# 0 0: disable smi event. 1: enable smi event via pme# or sirq if gpio50_smi_st is set. gpio5 smi status register ? offset a9h bit name r/w reset default description 7 gpio57_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio57 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 6 gpio56_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio56 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 5 gpio55_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio55 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 4 gpio54_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio54 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 3 gpio53_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio53 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 2 gpio52_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio52 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 1 gpio51_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio51 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. 0 gpio50_smi_st r/w lreset# 0 0: no smi event. 1: a smi event will set if gpio50 input is changed. this bit is available in input mode. write ?1? to this bit will clear the status. gpio6 output enable register ? offset 90h bit name r/w reset default description 7 gpio67_oe r/w lreset# 0 0: gpio67 is in input mode. 1: gpio67 is in output mode. 6 gpio66_oe r/w lreset# 0 0: gpio66 is in input mode. 1: gpio65 is in output mode. 5 gpio65_oe r/w lreset# 0 0: gpio65 is in input mode. 1: gpio65 is in output mode. 4 gpio64_oe r/w lreset# 0 0: gpio64 is in input mode. 1: gpio64 is in output mode. 3 gpio63_oe r/w lreset# 0 0: gpio63 is in input mode. 1: gpio63 is in output mode. 2 gpio62_oe r/w lreset# 0 0: gpio62 is in input mode. 1: gpio62 is in output mode.
F81867 dec, 2011 v0.12p 274 1 gpio61_oe r/w lreset# 0 0: gpio61 is in input mode. 1: gpio61 is in output mode. 0 gpio60_oe r/w lreset# 0 0: gpio60 is in input mode. 1: gpio60 is in output mode. gpio6 output data register ? offset 91h bit name r/w reset default description 7 gpio67_val r/w lreset# 1 0: gpio67 outputs 0 when in output mode. 1: gpio67 outputs 1 when in output mode. 6 gpio66_val r/w lreset# 1 0: gpio66 outputs 0 when in output mode. 1: gpio66 outputs 1 when in output mode. 5 gpio65_val r/w lreset# 1 0: gpio65 outputs 0 when in output mode. 1: gpio65 outputs 1 when in output mode. 4 gpio64_val r/w lreset# 1 0: gpio64 outputs 0 when in output mode. 1: gpio64 outputs 1 when in output mode. 3 gpio63_val r/w lreset# 1 0: gpio63 outputs 0 when in output mode. 1: gpio63 outputs 1 when in output mode. 2 gpio62_val r/w lreset# 1 0: gpio62 outputs 0 when in output mode. 1: gpio62 outputs 1 when in output mode. 1 gpio61_val r/w lreset# 1 0: gpio61 outputs 0 when in output mode. 1: gpio61 outputs 1 when in output mode. 0 gpio60_val r/w lreset# 1 0: gpio60 outputs 0 when in output mode. 1: gpio60 outputs 1 when in output mode. gpio6 pin status register ? offset 92h bit name r/w reset default description 7 gpio67_in r - - the pin status of s5#/gpio67. 6 gpio66_in r - - the pin status of dpwrok/gpio66. 5 gpio65_in r - - the pin status of pme#/gpio65. 4 gpio64_in r - - the pin status of gpio64dskchg#/dsr5#. 3 gpio63_in r - - the pin status of gpio63/wpt#/dtr5#/pwm3. 2 gpio62_in r - - the pin status of gpio62/index#/cts5#/pwm2. 1 gpio61_in r - - the pin status of gpio61/trk0#/ri5#/pwm1. 0 gpio60_in r - - the pin status of gpio60/rdata#/dcd5#/pwm0. gpio6 drive enable register ? offset 93h bit name r/w reset default description 7 gpio67_drv_en r/w lreset# 0 0: gpio67 is open drain in output mode. 1: gpio67 is push pull in output mode. 6 gpio66_drv_en r/w lreset# 0 0: gpio66 is open drain in output mode. 1: gpio66 is push pull in output mode. 5 gpio65_drv_en r/w lreset# 0 0: gpio65 is open drain in output mode. 1: gpio65 is push pull in output mode. 4 gpio64_drv_en r/w lreset# 0 0: gpio64 is open drain in output mode. 1: gpio64 is push pull in output mode.
F81867 dec, 2011 v0.12p 275 3 gpio63_drv_en r/w lreset# 0 0: gpio63 is open drain in output mode. 1: gpio63 is push pull in output mode. 2 gpio62_drv_en r/w lreset# 0 0: gpio62 is open drain in output mode. 1: gpio62 is push pull in output mode. 1 gpio61_drv_en r/w lreset# 0 0: gpio61 is open drain in output mode. 1: gpio61 is push pull in output mode. 0 gpio60_drv_en r/w lreset# 0 0: gpio60 is open drain in output mode. 1: gpio60 is push pull in output mode. gpio7 output enable register ? offset 80h bit name r/w reset default description 7 gpio77_oe r/w lreset# 0 0: gpio77 is in input mode. 1: gpio77 is in output mode. 6 gpio76_oe r/w lreset# 0 0: gpio76 is in input mode. 1: gpio75 is in output mode. 5 gpio75_oe r/w lreset# 0 0: gpio75 is in input mode. 1: gpio75 is in output mode. 4 gpio74_oe r/w lreset# 0 0: gpio74 is in input mode. 1: gpio74 is in output mode. 3 gpio73_oe r/w lreset# 0 0: gpio73 is in input mode. 1: gpio73 is in output mode. 2 gpio72_oe r/w lreset# 0 0: gpio72 is in input mode. 1: gpio72 is in output mode. 1 gpio71_oe r/w lreset# 0 0: gpio71 is in input mode. 1: gpio71 is in output mode. 0 gpio70_oe r/w lreset# 0 0: gpio70 is in input mode. 1: gpio70 is in output mode. gpio7 output data register ? offset 81h bit name r/w reset default description 7 gpio77_val r/w lreset# 1 0: gpio77 outputs 0 when in output mode. 1: gpio77 outputs 1 when in output mode. 6 gpio76_val r/w lreset# 1 0: gpio76 outputs 0 when in output mode. 1: gpio76 outputs 1 when in output mode. 5 gpio75_val r/w lreset# 1 0: gpio75 outputs 0 when in output mode. 1: gpio75 outputs 1 when in output mode. 4 gpio74_val r/w lreset# 1 0: gpio74 outputs 0 when in output mode. 1: gpio74 outputs 1 when in output mode. 3 gpio73_val r/w lreset# 1 0: gpio73 outputs 0 when in output mode. 1: gpio73 outputs 1 when in output mode. 2 gpio72_val r/w lreset# 1 0: gpio72 outputs 0 when in output mode. 1: gpio72 outputs 1 when in output mode. 1 gpio71_val r/w lreset# 1 0: gpio71 outputs 0 when in output mode. 1: gpio71 outputs 1 when in output mode. 0 gpio70_val r/w lreset# 1 0: gpio70 outputs 0 when in output mode. 1: gpio70 outputs 1 when in output mode.
F81867 dec, 2011 v0.12p 276 gpio7 pin status register ? offset 82h bit name r/w reset default description 7 gpio77_in r - - the pin status of gpio77/stb#. 6 gpio76_in r - - the pin status of gpio76/afd#. 5 gpio75_in r - - the pin status of gpio75/err#. 4 gpio74_in r - - the pin status of gpio74/init#. 3 gpio73_in r - - the pin status of gpio73/slin#. 2 gpio72_in r - - the pin status of gpio72/ack#. 1 gpio71_in r - - the pin status of gpio71/busy. 0 gpio70_in r - - the pin status of gpio70/pe/fanctrl3. gpio7 drive enable register ? offset 83h bit name r/w reset default description 7 gpio77_drv_en r/w lreset# 0 0: gpio77 is open drain in output mode. 1: gpio77 is push pull in output mode. 6 gpio76_drv_en r/w lreset# 0 0: gpio76 is open drain in output mode. 1: gpio76 is push pull in output mode. 5 gpio75_drv_en r/w lreset# 0 0: gpio75 is open drain in output mode. 1: gpio75 is push pull in output mode. 4 gpio74_drv_en r/w lreset# 0 0: gpio74 is open drain in output mode. 1: gpio74 is push pull in output mode. 3 gpio73_drv_en r/w lreset# 0 0: gpio73 is open drain in output mode. 1: gpio73 is push pull in output mode. 2 gpio72_drv_en r/w lreset# 0 0: gpio72 is open drain in output mode. 1: gpio72 is push pull in output mode. 1 gpio71_drv_en r/w lreset# 0 0: gpio71 is open drain in output mode. 1: gpio71 is push pull in output mode. 0 gpio70_drv_en r/w lreset# 0 0: gpio70 is open drain in output mode. 1: gpio70 is push pull in output mode. gpio8 output enable register ? offset 88h bit name r/w reset default description 7 gpio87_oe r/w lreset# 0 0: gpio87 is in input mode. 1: gpio87 is in output mode. 6 gpio86_oe r/w lreset# 0 0: gpio86 is in input mode. 1: gpio85 is in output mode. 5 gpio85_oe r/w lreset# 0 0: gpio85 is in input mode. 1: gpio85 is in output mode. 4 gpio84_oe r/w lreset# 0 0: gpio84 is in input mode. 1: gpio84 is in output mode. 3 gpio83_oe r/w lreset# 0 0: gpio83 is in input mode. 1: gpio83 is in output mode. 2 gpio82_oe r/w lreset# 0 0: gpio82 is in input mode. 1: gpio82 is in output mode.
F81867 dec, 2011 v0.12p 277 1 gpio81_oe r/w lreset# 0 0: gpio81 is in input mode. 1: gpio81 is in output mode. 0 gpio80_oe r/w lreset# 0 0: gpio80 is in input mode. 1: gpio80 is in output mode. gpio8 output data register ? offset 89h bit name r/w reset default description 7 gpio87_val r/w lreset# 1 0: gpio87 outputs 0 when in output mode. 1: gpio87 outputs 1 when in output mode. 6 gpio86_val r/w lreset# 1 0: gpio86 outputs 0 when in output mode. 1: gpio86 outputs 1 when in output mode. 5 gpio85_val r/w lreset# 1 0: gpio85 outputs 0 when in output mode. 1: gpio85 outputs 1 when in output mode. 4 gpio84_val r/w lreset# 1 0: gpio84 outputs 0 when in output mode. 1: gpio84 outputs 1 when in output mode. 3 gpio83_val r/w lreset# 1 0: gpio83 outputs 0 when in output mode. 1: gpio83 outputs 1 when in output mode. 2 gpio82_val r/w lreset# 1 0: gpio82 outputs 0 when in output mode. 1: gpio82 outputs 1 when in output mode. 1 gpio81_val r/w lreset# 1 0: gpio81 outputs 0 when in output mode. 1: gpio81 outputs 1 when in output mode. 0 gpio80_val r/w lreset# 1 0: gpio80 outputs 0 when in output mode. 1: gpio80 outputs 1 when in output mode. gpio8 pin status register ? offset 8ah bit name r/w reset default description 7 gpio87_in r - - the pin status of gpio87/pd7. 6 gpio86_in r - - the pin status of gpio86/pd6. 5 gpio85_in r - - the pin status of gpio85/pd5. 4 gpio84_in r - - the pin status of gpio84/pd4. 3 gpio83_in r - - the pin status of gpio83/pd3. 2 gpio82_in r - - the pin status of gpio82/pd2. 1 gpio81_in r - - the pin status of gpio81/pd1. 0 gpio80_in r - - the pin status of gpio80/pd0. gpio8 drive enable register ? offset 8bh bit name r/w reset default description 7 gpio87_drv_en r/w lreset# 0 0: gpio87 is open drain in output mode. 1: gpio87 is push pull in output mode. 6 gpio86_drv_en r/w lreset# 0 0: gpio86 is open drain in output mode. 1: gpio86 is push pull in output mode. 5 gpio85_drv_en r/w lreset# 0 0: gpio85 is open drain in output mode. 1: gpio85 is push pull in output mode.
F81867 dec, 2011 v0.12p 278 4 gpio84_drv_en r/w lreset# 0 0: gpio84 is open drain in output mode. 1: gpio84 is push pull in output mode. 3 gpio83_drv_en r/w lreset# 0 0: gpio83 is open drain in output mode. 1: gpio83 is push pull in output mode. 2 gpio82_drv_en r/w lreset# 0 0: gpio82 is open drain in output mode. 1: gpio82 is push pull in output mode. 1 gpio81_drv_en r/w lreset# 0 0: gpio81 is open drain in output mode. 1: gpio81 is push pull in output mode. 0 gpio80_drv_en r/w lreset# 0 0: gpio80 is open drain in output mode. 1: gpio80 is push pull in output mode. 7.20.10 gpio8x scan code registers gpio8 make code 0 register ? offset d8h bit name r/w reset default description 7-0 gp_make_code0 r/w 5vsb 0 this byte is used to assert make code when scan code event 0 occur. the scan code events will set kbc obf and put their make/break code into kbc output buffer. the break code is make code + 0x80 and this function is implemented by c. the source of event is gpio80. gpio8 make code 1 register ? offset d9h bit name r/w reset default description 7-0 gp_make_code1 r/w 5vsb 0 this byte is used to assert make code when scan code event 1 occur. the scan code events will set kbc obf and put their make/break code into kbc output buffer. the break code is make code + 0x80 and this function is implemented by c. the source of event is gpio81. gpio8 make code 2 register ? offset dah bit name r/w reset default description 7-0 gp_make_code2 r/w 5vsb 0 this byte is used to assert make code when scan code event 2 occur. the scan code events will set kbc obf and put their make/break code into kbc output buffer. the break code is make code + 0x80 and this function is implemented by c. the source of event is gpio82. gpio8 make code 3 register ? offset dbh bit name r/w reset default description 7-0 gp_make_code3 r/w 5vsb 0 this byte is used to assert make code when scan code event 3 occur. the scan code events will set kbc obf and put their make/break code into kbc output buffer. the break code is make code + 0x80 and this function is implemented by c. the source of event is gpio83.
F81867 dec, 2011 v0.12p 279 gpio8 make code 4 register ? offset dch bit name r/w reset default description 7-0 gp_make_code4 r/w 5vsb 0 this byte is used to assert make code when scan code event 4 occur. the scan code events will set kbc obf and put their make/break code into kbc output buffer. the break code is make code + 0x80 and this function is implemented by c. the source of event is gpio84. gpio8 make code 5 register ? offset ddh bit name r/w reset default description 7-0 gp_make_code5 r/w 5vsb 0 this byte is used to assert make code when scan code event 5 occur. the scan code events will set kbc obf and put their make/break code into kbc output buffer. the break code is make code + 0x80 and this function is implemented by c. the source of event is gpio85. gpio8 make code 6 register ? offset deh bit name r/w reset default description 7-0 gp_make_code6 r/w 5vsb 0 this byte is used to assert make code when scan code event 6 occur. the scan code events will set kbc obf and put their make/break code into kbc output buffer. the break code is make code + 0x80 and this function is implemented by c. the source of event is gpio86. gpio8 make code 7 register ? offset dfh bit name r/w reset default description 7-0 gp_make_code7 r/w 5vsb 0 this byte is used to assert make code when scan code event 7 occur. the scan code events will set kbc obf and put their make/break code into kbc output buffer. the break code is make code + 0x80 and this function is implemented by c. the source of event is gpio87. gpio8 pre-code 0 register ? offset c8h bit name r/w reset default description 7-0 gp_pre_code0 r/w 5vsb 0xe0 this byte is used to assert a pre-code before the make/break code when it is enabled. gpio8 pre-code 1 register ? offset c9h bit name r/w reset default description 7-0 gp_pre_code1 r/w 5vsb 0xe0 this byte is used to assert a pre-code before the make/break code when it is enabled. gpio8 pre-code 2 register ? offset cah bit name r/w reset default description 7-0 gp_pre_code2 r/w 5vsb 0xe0 this byte is used to assert a pre-code before the make/break code when it is enabled. gpio8 pre-code 3 register ? offset cbh bit name r/w reset default description 7-0 gp_pre_code3 r/w 5vsb 0xe0 this byte is used to assert a pre-code before the make/break code when it is enabled.
F81867 dec, 2011 v0.12p 280 gpio8 pre-code 4 register ? offset cch bit name r/w reset default description 7-0 gp_pre_code4 r/w 5vsb 0xe0 this byte is used to assert a pre-code before the make/break code when it is enabled. gpio8 pre-code 5 register ? offset cdh bit name r/w reset default description 7-0 gp_pre_code5 r/w 5vsb 0xe0 this byte is used to assert a pre-code before the make/break code when it is enabled. gpio8 pre-code 6 register ? offset ceh bit name r/w reset default description 7-0 gp_pre_code6 r/w 5vsb 0xe0 this byte is used to assert a pre-code before the make/break code when it is enabled. gpio8 pre-code 7 register ? offset cfh bit name r/w reset default description 7-0 gp_pre_code7 r/w 5vsb 0xe0 this byte is used to assert a pre-code before the make/break code when it is enabled. gpio8 scan code 0 control register ? offset b8h bit name r/w reset default description 7 gp0_ctrl_en r/w 5vsb 0 set ?1? will assert a left ?ctrl? key code first when scan code event occurs. 6 gp0_alt_en r/w 5vsb 0 set ?1? will assert a left ?alt? key code first when scan code event occurs. 5 gp0_shift_en r/w 5vsb 0 set ?1? will assert a left ?shift? key code first when scan code event occurs. 4 gp0_pre_en r/w 5vsb 0 set ?1? will assert a left pre-code first when scan code 0 event occurs. when multiple keys are enabled, the sequence is ?ctrl? ? ?alt? ? ?shift? ? pre-code ? make/break code. 3-2 gp0_delay_time r/w 5vsb 0 the delay time for repeat make code could be user defined. c reads this register to determine the delay time. 0 gp0_rep_time r/w 5vsb 0 the repeat time for repeat make code could be user defined. c reads this register to determine the delay time. gpio8 scan code 1 control register ? offset b9h bit name r/w reset default description 7 gp1_ctrl_en r/w 5vsb 0 set ?1? will assert a left ?ctrl? key code first when scan code event occurs. 6 gp1_alt_en r/w 5vsb 0 set ?1? will assert a left ?alt? key code first when scan code event occurs. 5 gp1_shift_en r/w 5vsb 0 set ?1? will assert a left ?shift? key code first when scan code event occurs. 4 gp1_pre_en r/w 5vsb 0 set ?1? will assert a left pre-code first when scan code 0 event occurs. when multiple keys are enabled, the sequence is ?ctrl? ? ?alt? ? ?shift? ? pre-code ? make/break code. 3-2 gp1_delay_time r/w 5vsb 0 the delay time for repeat make code could be user defined. c reads this register to determine the delay time. 0 gp1_rep_time r/w 5vsb 0 the repeat time for repeat make code could be user defined. c reads this register to determine the delay time.
F81867 dec, 2011 v0.12p 281 gpio8 scan code 2 control register ? offset bah bit name r/w reset default description 7 gp2_ctrl_en r/w 5vsb 0 set ?1? will assert a left ?ctrl? key code first when scan code event occurs. 6 gp2_alt_en r/w 5vsb 0 set ?1? will assert a left ?alt? key code first when scan code event occurs. 5 gp2_shift_en r/w 5vsb 0 set ?1? will assert a left ?shift? key code first when scan code event occurs. 4 gp2_pre_en r/w 5vsb 0 set ?1? will assert a left pre-code first when scan code 0 event occurs. when multiple keys are enabled, the sequence is ?ctrl? ? ?alt? ? ?shift? ? pre-code ? make/break code. 3-2 gp2_delay_time r/w 5vsb 0 the delay time for repeat make code could be user defined. c reads this register to determine the delay time. 0 gp2_rep_time r/w 5vsb 0 the repeat time for repeat make code could be user defined. c reads this register to determine the delay time. gpio8 scan code 3 control register ? offset bbh bit name r/w reset default description 7 gp3_ctrl_en r/w 5vsb 0 set ?1? will assert a left ?ctrl? key code first when scan code event occurs. 6 gp3_alt_en r/w 5vsb 0 set ?1? will assert a left ?alt? key code first when scan code event occurs. 5 gp3_shift_en r/w 5vsb 0 set ?1? will assert a left ?shift? key code first when scan code event occurs. 4 gp3_pre_en r/w 5vsb 0 set ?1? will assert a left pre-code first when scan code 0 event occurs. when multiple keys are enabled, the sequence is ?ctrl? ? ?alt? ? ?shift? ? pre-code ? make/break code. 3-2 gp3_delay_time r/w 5vsb 0 the delay time for repeat make code could be user defined. c reads this register to determine the delay time. 0 gp3_rep_time r/w 5vsb 0 the repeat time for repeat make code could be user defined. c reads this register to determine the delay time. gpio8 scan code 4 control register ? offset bch bit name r/w reset default description 7 gp4_ctrl_en r/w 5vsb 0 set ?1? will assert a left ?ctrl? key code first when scan code event occurs. 6 gp4_alt_en r/w 5vsb 0 set ?1? will assert a left ?alt? key code first when scan code event occurs. 5 gp4_shift_en r/w 5vsb 0 set ?1? will assert a left ?shift? key code first when scan code event occurs. 4 gp4_pre_en r/w 5vsb 0 set ?1? will assert a left pre-code first when scan code 0 event occurs. when multiple keys are enabled, the sequence is ?ctrl? ? ?alt? ? ?shift? ? pre-code ? make/break code. 3-2 gp4_delay_time r/w 5vsb 0 the delay time for repeat make code could be user defined. c reads this register to determine the delay time. 0 gp4_rep_time r/w 5vsb 0 the repeat time for repeat make code could be user defined. c reads this register to determine the delay time. gpio8 scan code 5 control register ? offset bdh bit name r/w reset default description 7 gp5_ctrl_en r/w 5vsb 0 set ?1? will assert a left ?ctrl? key code first when scan code event occurs. 6 gp5_alt_en r/w 5vsb 0 set ?1? will assert a left ?alt? key code first when scan code event occurs. 5 gp5_shift_en r/w 5vsb 0 set ?1? will assert a left ?shift? key code first when scan code event occurs. 4 gp5_pre_en r/w 5vsb 0 set ?1? will assert a left pre-code first when scan code 0 event occurs. when multiple keys are enabled, the sequence is ?ctrl? ? ?alt? ? ?shift? ? pre-code ? make/break code.
F81867 dec, 2011 v0.12p 282 3-2 gp5_delay_time r/w 5vsb 0 the delay time for repeat make code could be user defined. c reads this register to determine the delay time. 0 gp5_rep_time r/w 5vsb 0 the repeat time for repeat make code could be user defined. c reads this register to determine the delay time. gpio8 scan code 6 control register ? offset beh bit name r/w reset default description 7 gp6_ctrl_en r/w 5vsb 0 set ?1? will assert a left ?ctrl? key code first when scan code event occurs. 6 gp6_alt_en r/w 5vsb 0 set ?1? will assert a left ?alt? key code first when scan code event occurs. 5 gp6_shift_en r/w 5vsb 0 set ?1? will assert a left ?shift? key code first when scan code event occurs. 4 gp6_pre_en r/w 5vsb 0 set ?1? will assert a left pre-code first when scan code 0 event occurs. when multiple keys are enabled, the sequence is ?ctrl? ? ?alt? ? ?shift? ? pre-code ? make/break code. 3-2 gp6_delay_time r/w 5vsb 0 the delay time for repeat make code could be user defined. c reads this register to determine the delay time. 0 gp6_rep_time r/w 5vsb 0 the repeat time for repeat make code could be user defined. c reads this register to determine the delay time. gpio8 scan code 7 control register ? offset bfh bit name r/w reset default description 7 gp7_ctrl_en r/w 5vsb 0 set ?1? will assert a left ?ctrl? key code first when scan code event occurs. 6 gp7_alt_en r/w 5vsb 0 set ?1? will assert a left ?alt? key code first when scan code event occurs. 5 gp7_shift_en r/w 5vsb 0 set ?1? will assert a left ?shift? key code first when scan code event occurs. 4 gp7_pre_en r/w 5vsb 0 set ?1? will assert a left pre-code first when scan code 0 event occurs. when multiple keys are enabled, the sequence is ?ctrl? ? ?alt? ? ?shift? ? pre-code ? make/break code. 3-2 gp7_delay_time r/w 5vsb 0 the delay time for repeat make code could be user defined. c reads this register to determine the delay time. 0 gp7_rep_time r/w 5vsb 0 the repeat time for repeat make code could be user defined. c reads this register to determine the delay time. gpio7 function select 1 register ? offset ach bit name r/w reset default description 7-6 gpio73_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio73 is. 5-4 gpio72_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio72 is. 3-2 gpio71_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio71 is. 1-0 gpio70_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio70 is. gpio7 function select register ? offset adh bit name r/w reset default description 7-6 gpio77_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio77 is.
F81867 dec, 2011 v0.12p 283 5-4 gpio76_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio76 is. 3-2 gpio75_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio75 is. 1-0 gpio74_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio74 is. gpio8 function select 1 register ? offset aeh bit name r/w reset default description 7-6 gpio83_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio83 is. 5-4 gpio82_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio82 is. 3-2 gpio81_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio81 is. 1-0 gpio80_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio80 is. gpio8 function select register ? offset afh bit name r/w reset default description 7-6 gpio87_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio87 is. 5-4 gpio86_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio86 is. 3-2 gpio85_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio85 is. 1-0 gpio84_func_sel r/w 5vsb 0 these two bits are used for host and c communication. c could used these two bits to decide which function gopio84 is. 7.20.11 kbc c side register (base address 0x2200, 256 bytes) output buffer register ? offset 00h bit name r/w reset default description 7-0 c_output_buf r/w 5vsb 0 the code c write to kbc. after write this byte, kbc obf will be set. kbc control register ? offset 01h bit name r/w reset default description 7 c_kb_obf r/w 5vsb 0 this bit is set by writing c_output_buf when mo_date_en is disabled. it will auto cleared when the host read 0x60 port. 6 c_mo_obf r/w 5vsb 0 this bit is set by write c_output_buf when mo_date_en is enabled. it will auto cleared when the host read 0x60 port. 5 c_dis_obf r/w 5vsb 0 set ?1? to disable ps/ 2 to set obf flag. 4 mo_data_en r/w 5vsb 0 0: c_output_buf is the keyboard data. 1: c_output_buf is the mouse data.
F81867 dec, 2011 v0.12p 284 3 host_dis_mo_clk r 5vsb 0 this bit represents the status of host disable mouse clock signal. 2 host_dis_kb_clk r 5vsb 0 this bit represents the status of host disable keyboard clock signal. 1 c_dis_mo_clk r/w 5vsb 0 set ?1? to disable ps/2 mouse interface. ps2_ctrl_en switch the disable signal between host_dis_mo_clk and c_dis_mo_clk. 0 c_dis_kb_clk r/w 5vsb 0 set ?1? to disable ps/2 keyboard interface. ps2_ctrl_en switch the disable signal between host_dis_kb_clk and c_dis_kb_clk. kbc status register ? offset 02h bit name r/w reset default description 7-0 kbc_sts r 5vsb - the status of kbc. same as 0x64 port of host side. ps/2 interrupt enable register ? offset 03h bit name r/w reset default description 7 kbc_st_int_en r/w 5vsb 0 0: disable kbc status interrupt. 1: enable kbc status interrupt. kbc_sts change will assert interrupt to c. 6 reserved - - - reserved. 5 mo_rd_in_en r/w 5vsb 0 0: disable read mouse data interrupt. 1: enable read mouse data interrupt. host read mouse data will assert interrupt to c. 4 kb_rd_in_en r/w 5vsb 0 0: disable read keyboard data interrupt. 1: enable read keyboard data interrupt. host read mouse data will assert interrupt to c. 3 mo_wr_int_en r/w 5vsb 0 0: disable ps/2 mouse write command interrupt. 1: enable ps/2 mouse interface interrup t. an interrupt will be asserted to c when the host write command to ps/2 mouse which will set mo_wr_byte_st. 2 kb_wr_int_en r/w 5vsb 0 0: disable ps/2 keyboard write command interrupt. 1: enable ps/2 keyboard interface interrup t. an interrupt will be asserted to c when host write command to ps/2 keyboard which will set kb_wr_byte_st. 1 mo_rcv_int_en r/w 5vsb 0 0: disable ps/2 mouse inte rface receiving interrupt. 1: enable ps/2 mouse interface receiving interrupt. an interrupt will be asserted to c when a byte is received which will set mo_rcv_byte_st. 0 kb_rcv_int_en r/w 5vsb 0 0: disable ps/2 keyboard interface receiving interrupt. 1: enable ps/2 keyboard interface receiving interrupt. an interrupt will be asserted to c when a byte is received which will set kb_rcv_byte_st. ps/2 receiving status register ? offset 04h bit name r/w reset default description 7 kbc_st_chg_st r/wc 5vsb 0 this bit will be set when kbc_sts changes. 6 reserved - - - reserved. 5 mo_rd_st r/wc 5vsb 0 this bit will be set when host read mouse data. 4 kb_rd_st r/wc 5vsb 0 this bit will be set when host read keyboard data. 3 mo_wr_byte_st r/wc 5vsb 0 this bit will be set when host write data to mouse. write ?1? to clear. 2 kb_wr_byte_st r/wc 5vsb 0 this bit will be set when host write data to keyboard. write ?1? to clear.
F81867 dec, 2011 v0.12p 285 1 mo_rcv_byte_st r/wc 5vsb 0 this bit will be set when ps/2 mouse interface receive a byte. write ?1? to clear. 0 kb_rcv_byte_st r/wc 5vsb 0 this bit will be set when ps/2 keyboard interface receive a byte. write ?1? to clear. ps/2 keyboard unmapped code register ? offset 05h bit name r/w reset default description 7-0 kb_unmapped_co de r 5vsb 0 this is the raw data received from keyboard. not translated into scan code set 1. ps/2 keyboard data register ? offset 06h bit name r/w reset default description 7-0 kb_code r 5vsb 0 the keyboard data after translated into scan code set 1. ps/2 mouse data register ? offset 07h bit name r/w reset default description 7-0 mo_code r 5vsb 0 the mouse data receive from a mouse. ps/2 host output register ? offset 08h bit name r/w reset default description 7-0 ps2_host_dout r 5vsb 0 this is the output data host writ e to ps/2 keyboard/mouse. check mo_wr_byte_st/kb_wr_byte_st to determine the data is for keyboard or mouse. ps/2 c output register ? offset 09h bit name r/w reset default description 7-0 ps2_ c_dout r/w 5vsb 0 this is the output data c wants to write to ps/2 keyboard/mouse. ps/2 control register ? offset 0ah bit name r/w reset default description 7 c_cmd_rst w 5vsb - write ?1? to assert a kbc command reset to ps/2. 6 c_clr_ibf w 5vsb - write ?1? to clear ibf. 5 c_clr_swap w 5vsb - write ?1? to disable keyboard/mouse swap. 4 c_set_swap r/w 5vsb - write ?1? to enable keyboard/mouse swap. this bit will return the status of swap enable. 3 c_mo_rd w 5vsb - when ps2_ctrl_en is set to ?1?, write ?1? to this bit will assert a mouse read signal to ps/2 block to reset the ps/2 state machine. 2 c_kb_rd w 5vsb - when ps2_ctrl_en is set to ?1?, write ?1? to this bit will assert a keyboard read signal to ps/2 block to reset the ps/2 state machine. 1 c_mo_wr w 5vsb - when ps2_ctrl_en is set to ?1?, write ?1? to this bit will assert a mouse write signal to ps/2 block and the data is the ps2_ c_dout. 0 c_kb_wr w 5vsb - when ps2_ctrl_en is set to ?1?, write ?1? to this bit will assert a keyboard write signal to ps/2 block and the data is the ps2_ c_dout.
F81867 dec, 2011 v0.12p 286 ps/2 reset control register ? offset 0bh bit name r/w reset default description 7-6 reserved - - - reserved. 5 lreset_st r 5vsb 0 the status of lreset#. 4 kbc_s3 r 5vsb 0 the s3 condition status for ps/2. 3-2 reserved - - - reserved. 1 c_lreset_n r/w 5vsb 1 when ps2_ctrl_en is set, c could use the bit to reset kbc block. 0 c_kbc_s3 r/w 5vsb 0 when ps2_ctrl_en is set, c could use the bit to emulate a s3 condition for wakeup function. ps/2 reset control register ? offset 0ch bit name r/w reset default description 7 p_mdata_in r - - pin status of mdata. 6 p_mclk_in r - - pin status of mclk. 5 p_kdata_in r - - pin status of kdata. 4 p_kclk_in r - - pin status of kclk. 3 c_mdata_out r/w 5vsb 1 when c_mo_pin_en is set, c uses this bit to control the mdata. 2 c_mclk_out r/w 5vsb 1 when c_mo_pin_en is set, c uses this bit to control the mclk. 1 c_kdata_out r/w 5vsb 1 when c_kb_pin_en is set, c uses this bit to control the kdata. 0 c_kclk_out r/w 5vsb 1 when c_kb_pin_en is set, c uses this bit to control the kclk. ps/2 control register ? offset 0fh bit name r/w reset default description 7-4 reserved - - - reserved. 3 c_kb_pin_en r/w 5vsb 0 set ?1? to control kclk/kdata by c_kclk_out and c_kdata_out. 2 c_mo_pin_en r/w 5vsb 0 set ?1? to control mclk/mdata by c_mclk_out and c_mdata_out. 1 ps2_ctrl_en r/w 5vsb 0 0: disable c to control ps/2 interface. 1: enable c to control ps/2 interface. c could assert read/write signal to ps/2 block if pseudo_8048_en is ?0?. 0 pseudo_8048_en r/w 5vsb 0 set ?1? to emulate 8048 to response kbc command. when this bit is set, any read/write signal for ps/2 is block. c is responsible to return the data to keyboard controller. 7.20.12 acpi c side register (base address 0x2300, 256 bytes) acpi pin status 1 register ? offset 03h bit name r/w reset default description 7 reserved - - - reserved. 6 rsmrst_n_in r - 0 pin status of rsmrst#. 5 pwrok_in r - 0 pin status of pwrok. 4 pson_n_in r - 0 pin status of ps_on#. 3 pwsout_n_in r - 0 pin status of pwsout#.
F81867 dec, 2011 v0.12p 287 2 pme_n_in r - 0 pin status of pme#. 1 erp_ctrl1_in r - 0 pin status of erp_ctrl1#. 0 erp_ctrl0_in r - 0 pin status of erp_ctrl0#. acpi pin status 2 register ? offset 04h bit name r/w reset default description 7 reserved - - - reserved. 6 lreset_n_in r - - pin status of lreset#. 5 vsb3vok r - 0 the vsb3v power is ready. 4 vdd3vok r - 0 the vdd3v power is ready. 3 s5_n_in r - 0 pin status of s5#. 2 s3_n_in r - 0 pin status of s3#. 1 pwsin_n_in r - 0 pin status of pwsin#. 0 atxpg_in r - 0 pin status of atxpg. acpi pin status 3 register ? offset 05h bit name r/w reset default description 7-4 reserved - - - reserved. 3 dpwrok_in r - 0 pin status of dpwrok. 2 sus_ack_n_in r - 0 pin status of sus_ack#. 1 sus_warn_n_in r - 0 pin status of sus_warn#. 0 slp_sus_n_in r - 0 pin status of slp_sus. acpi input pin control 1 register ? offset 07h bit name r/w reset default description 7-4 reserved - - - reserved. 3 c_atxpg r/w 5vsb 1 c control this bit to and-ed with atxpg pin for internal atxpg signal. 2 c_s3_n r/w 5vsb 1 c control this bit to and-ed with s3# pin for internal s3# signal. 1 c_s5_n r/w 5vsb 1 c control this bit to and-ed with s5# pin for internal s5# signal. 0 c_pwsin_n r/w 5vsb 1 c control this bit to and-ed with pwsi n# pin for internal pwsin# signal. acpi input pin control 2 register ? offset 08h bit name r/w reset default description 7-2 reserved - - - reserved. 1 c_sus_warn_n r/w 5vsb 1 c control this bit to and-ed with sus_warn# pin for internal sus_warn# signal. 0 c_slp_sus_n r/w 5vsb 1 c control this bit to and-ed with sl p_sus# pin for internal slp_sus# signal.
F81867 dec, 2011 v0.12p 288 kb pme control register ? offset 0eh bit name r/w reset default description 7-6 reserved - 5vsb - reserved. 5 ms_pme_st r/wc 5vsb - this bit is the status of mouse pm e event. it is the same as the pme configuration register in host side. write ?1? will clear the status. 4 kb_pme_st r/wc 5vsb - this bit is the status of keyboard pme event. it is the same as the pme configuration register in host side. write ?1? will clear the status. 3-2 reserved - 5vsb - reserved. 1 ms_pme_en r/w 5vsb 0 0: disable mouse pme event. 1: enable mouse pme event. 0 kb_pme_en r/w 5vsb 0 0: disable keyboard pme event. 1: enable keyboard pme event. erp state control register ? offset 0fh bit name r/w reset default description 7 s3_back r/w 5vsb 0 c set this bit to inform host that the sy stem is return from deep s3 state. 6-2 reserved - - - reserved. 0 ds3_state r/w 5vsb 0 c set this bit to make acpi control signals entering deep s3 state. for example, led will output 0.25hz clock in deep s3 state. acpi deep s3 control register ? offset 0fh bit name r/w reset default description 7 s3_back r/w 5vsb 0 set ?1? to inform host the system is back from s3 state. 6-1 reserved - - - reserved. 0 ds3_state r/w 5vsb 0 set ?1? to enter deep s3 state. acpi interrupt enable register 1 ? offset 10h bit name r/w reset default description 7 lreset_st_int_e n r/w 5vsb 0 0: disable lreset# pin status interrupt. 1: enable lreset# pin status interrupt. an interrupt will assert to c if lreset# pin status change. 6 s5_st_int_en r/w 5vsb 0 0: disable s5 state interrupt. 1: enable s5 state interrupt. an interrupt will assert to c if system enter s5 state. 5 s3_st_int_en r/w 5vsb 0 0: disable s3 state interrupt. 1: enable s3 state interrupt. an interrupt will assert to c if system enter s3 state. 4 s0_st_int_en r/w 5vsb 0 0: disable s0 state interrupt. 1: enable s0 state interrupt. an interrupt will assert to c if system enter s0 state. 3 s5_int_en r/w 5vsb 0 0: disable s5# pin status interrupt. 1: enable s5# pin status interrup t. an interrupt will assert to c if s5# pin status change. 2 s3_int_en r/w 5vsb 0 0: disable s3# pin status interrupt. 1: enable s3# pin status interrup t. an interrupt will assert to c if s3# pin status change.
F81867 dec, 2011 v0.12p 289 1 pwsin_int_en r/w 5vsb 0 0: disable pwsin# pin status interrupt. 1: enable pwsin# pin status interrupt. an interrupt will assert to c if pwsin# pin status change. 0 atxpg_int_en r/w 5vsb 0 0: disable atxpg pin status interrupt. 1: enable atxpg pin status interrupt. an interrupt will assert to c if atxpg pin status change. acpi interrupt status register 1 ? offset 11h bit name r/w reset default description 7 lreset_int_st r/wc 5vsb 0 this bit will be set ?1? if lreset# pin status changes. write ?1? to clear. 6 s5_st_int_st r/wc 5vsb 0 this bit will be set ?1? if system enters s5 state. write ?1? to clear. 5 s3_st_int_st r/wc 5vsb 0 this bit will be set ?1? if system enters s3 state. write ?1? to clear. 4 s0_st_int_en r/wc 5vsb 0 this bit will be set ?1? if system enters s0 state. write ?1? to clear. 3 s5_int_st r/wc 5vsb 0 this bit will be set ?1? if s5# pin status changes. write ?1? to clear. 2 s3_int_st r/wc 5vsb 0 this bit will be set ?1? if s3# pin status changes. write ?1? to clear. 1 pwsin_int_st r/wc 5vsb 0 this bit will be set ?1? if pwsin# pin status changes. write ?1? to clear. 0 atxpg_int_st r/wc 5vsb 0 this bit will be set ?1? if atxpg pin status changes. write ?1? to clear. acpi interrupt enable register 2 ? offset 12h bit name r/w reset default description 7-2 reserved - - - reserved. 1 sus_warn_int_e n r/w 5vsb 0 0: disable sus_warn# pin status interrupt. 1: enable sus_warn## pin status interrupt. an interrupt will assert to c if sus_warn# pin status change. 0 slp_sus_int_en r/w 5vsb 0 0: disable slp_sus# pin status interrupt. 1: enable slp_sus# pin status inte rrupt. an interrupt will assert to c if slp_sus# pin status change. acpi interrupt status register 2 ? offset 13h bit name r/w reset default description 7-2 reserved - - - reserved. 1 sus_warn_int_st r/wc 5vsb 0 this bit will be set ?1? if sus_warn# pin status changes. write ?1? to clear. 0 slp_sus_int_st r/wc 5vsb 0 this bit will be set ?1? if slp_sus# pin status changes. write ?1? to clear. 7.20.13 configuration register (base address 0x2400, 256 bytes) chip id 1 register ? offset 20h (powered by i_vsb3v) bit name r/w reset default description 7-0 chip_id1 r - 0x10 chip id 1. chip id 2 register ? offset 21h (powered by i_vsb3v) bit name r/w reset default description
F81867 dec, 2011 v0.12p 290 7-0 chip_id2 r - 0x10 chip id 2. vendor id 1 register ? offset 23h (powered by i_vsb3v) bit name r/w reset default description 7-0 vendor_id1 r - 0x19 vendor id 1. vendor id 2 register ? offset 24h (powered by i_vsb3v) bit name r/w reset default description 7-0 vendor_id2 r - 0x34 vendor id 2. i2c address register ? offset 25h bit name r/w reset default description 7-1 i2c_addr r/w 5vsb 0 i2c address is used to r/w hardware monitor registers. the default address is determined by i2c_addr_trap power on strap pin. it could also be changed by write this byte with entry key 0x19, 0x34. the default value is 0x2e which indicates the address is 0x5c. 0 en_ara_mode r/w 5vsb 0 0: disable ara. 1: enable ara. clock select register ? offset 26h bit name r/w reset default description 7-6 clk_sel r/w 5vsb 0 the clock source of clkin. 00: clkin is 48mhz 10: clkin is 24mhz 01: clkin is 14.318mhz. 10: reserved. 5 reserved - reserved. 4 mo_pin_lvl_sel r/w 5vsb 0 mclk/mdata input level select. 0: ttl level. 1: low level with 0.6v low and 0.9v high. 3 pin76_lvl_sel r/w 5vsb 0 pin 76 input level select. 0: ttl level. 1: low level with 0.6v low and 0.9v high. 2 pin71_lvl_sel r/w 5vsb 0 pin 71 input level select. 0: ttl level. 1: low level with 0.6v low and 0.9v high. 1 pin68_lvl_sel r/w 5vsb 1 pin 68 input level select. 0: ttl level. 1: low level with 0.6v low and 0.9v high. 0 pin67_lvl_sel r/w 5vsb 1 pin 67 input level select. 0: ttl level. 1: low level with 0.6v low and 0.9v high.
F81867 dec, 2011 v0.12p 291 port select register ? offset 27h bit name r/w reset default description 7 ovp_mode r/w vbat* - 0: enable ovp function . 1: default is disabled; internal pull high 47k . the default value is determined by power on strap. 6 at_mode r/w 5vsb - 0: atx mode. 1: at mode. the default value is determined by power on strap. 5 gpio_dec_range r/w 3vcc 0 0: the gpio i/o space is 8-byte. 1: the gpio i/o space is 16-byte. 4 port_4e_en r/w 5vsb* - 0: the configuration register port is 2e/2f. 1: the configuration register port is 4e/4f. this register is power on trapped by rts1#/ config4e_2e. pull down to select port 2e/2f. this bit is accessed by host side only. 3-2 gpio_prog_sel r/w 5vsb 0 offset 2ch register select. 00: gpio0_en 01: gpio1_en 10: gpio2_en 11: c_port_en. bit 0 also select the offset 28h register: 0: multi-function select 1 register 1: multi-function select 2 register. 1 reserved - - - reserved 0 clk_tune_prog_ en r/w 3vcc 0 set ?1? to enable index 0x29, 0x2a, 0x2b, 0x2c function as clock fine tune register. multi-function select 1 register ? offset 28h (a vailable when gpio_prog_sel[0] = 0 ) bit name r/w reset default description 7 reserved - - - reserved 6 fdc_gp_en r/w 5vsb 1 pin 9 ~ 21 function select. these pins are controlled by fdc_gp_en, uart5_func_sel, uart6_func_sel and pwm_pin_en. to function as fdc, all these bits should be clear to ?0?. 5 lpt_gp_en r/w 5vsb 1 pin 102 ~ 118 function select. 0: functions as parallel port. 1: functions as gpio7/gpio8. 4 mo_i2c_en r/w 5vsb 0 pin 61, 62 function select. 0: ps/2 mouse interface mclk/mdata. 1: i2c scl/sda.
F81867 dec, 2011 v0.12p 292 3-2 uart5_func_sel r/w 5vsb 0 uart5 function select. 00: no uart5 pin. 01: simple uart: only sin5 and sout5 are available. pin 57 will be function as sout5 and pin 58 will function as sin5. 10: simple uart with rts#. in addition to simple uart, pin 59 will be function as rts5#. 11: full uart: pin 57 ~ 59, 17 ~ 21 will be function as uart pins. 1-0 uart6_func_sel r/w 5vsb 0 uart6 function select. 00: no uart6 pin. 01: simple uart: only sin6 and sout6 are available. pin 10 will be function as sout6 and pin 11 will be function as sin6. 10: simple uart with rts#. in addition to simple uart, pin 9 will be function as rts6#. 11: full uart: pin 9 ~ 16 will be function as uart pins. multi-function select 2 register ? offset 28h (a vailable when gpio_prog_sel[0] = 1 ) bit name r/w reset default description 7 reserved - - - reserved 6 c_p32_pin59_en r/w 5vsb 0 0: disable c p32 from pin 59. 1: enable c p32 from pin59. 5 c_p31_pin57_en r/w 5vsb 0 0: disable c p31 from pin 57. 1: enable c p31 from pin57. 4 c_p30_pin58_en r/w 5vsb 0 0: disable c p30 from pin 58. 1: enable c p30 from pin58. 3-2 reserved - - - reserved 1 cir_pin76_en r/w vbat 0 0: disable cirrx# from pin76. the pin function is alert#/gpio20/scl. 1: enable cirrx# from pin76. 0 cir_pin71_en r/w vbat 0 0: disable cirrx# from pin71. t he pin function is beep/gpio16/sda. 1: enable cirrx# from pin71. multi function select 3 register ? offset 29h (available when clk_ tune_prog_en = 0) bit name r/w reset default description 7-6 uart4_func_sel r/w 5vsb 0 uart4 function select. 00: no uart4 pin. pin 44 ~ 51 are all gpios. 01: simple uart: only sin4 and sout4 are available. pin 50 will be function as sout4 and pin 51 will be function as sin4. 10: simple uart with rts#. in addition to the simple uart, pin 48 will be function as rts4#. 11: full uart: pin 44 ~ 51 will be function as uart pins.
F81867 dec, 2011 v0.12p 293 5-4 ur3_func_sel r/w 5vsb 0 uart3 function select. 00: no uart3 pin. pin 36 ~ 43 are all gpios. 01: simple uart: only sin3 & sout3 ar e available. pin 42 will be function as sout3 and pin 43 will be function as sin3. 10: simple uart with rts#. in addition to simple uart, pin 40 will be function as rts3#. 11: full uart: pin 36 ~ 43 will be function as uart pins. 3 scl3_pin76_en r/w 5vsb 0 0: disable scl from pin 76. 1: enable scl from pin 76. there is only one slave in the current design, it is recommended to select only one pin for scl. when multi pins are selected, the priority of these bits is mo_i2c_en > scl_pin76_en > scl_pin67_en. 2 sda3_pin71_en r/w 5vsb 0 0: disable sda from pin 76. 1: enable sda from pin 76. there is only one slave in the current design, it is recommended to select only one pin for sda. when multi pins are selected, the priority of these bits is mo_i2c_en > sda_pin7 1_en > sda_pin68_en. 1 sda2_pin68_en r/w 5vsb 1 0: disable sda from pin 68. 1: enable sda from pin 68. there is only one slave in current desi gn, it is recommended to select only one pin for sda. when multi pins are sele cted, the priority of these bits is mo_i2c_en > sda_pin7 1_en > sda_pin68_en. 0 scl2_pin67_en r/w 5vsb 1 0: disable scl from pin 67. 1: enable scl from pin 67. there is only one slave in current desi gn, it is recommended to select only one pin for scl. when multi pins are sele cted, the priority of these bits is mo_i2c_en > scl_pin76_en > scl_pin67_en. 10hz clock divisor high byte ? offset 29h (available when clk_ tune_prog_en = 1) bit name r/w reset default description 7 fine_tune_start w - - write ?1? to start fine tune mechanism. the hardware will start to count 10 cycle internal 500khz clock with 48mhz clock. the count will present in index 0x2a, 0x2b. 6-4 reserved - - - reserved 3-0 clk10hz_div r/w vbat 4?h3 the divisor of 10hz clock. internal 10hz clock is used to generate wdt event. it is divided from 10khz clock and could be fine tune by change its divisor. multi function select 2 register ? offset 2ah (available when clk_ tune_prog_en = 0) bit name r/w reset default description 7 pwm3_lpt_pin_en r/w 5vsb 0 0: disable pwm3 from pin 110. 1: enable pwm3 from pin 110. 6 pwm2_lpt_pin_en r/w 5vsb 0 0: disable pwm2 from pin 109. 1: enable pwm2 from pin 109. 5 pwm1_lpt_pin_en r/w 5vsb 0 0: disable pwm1 from pin 108. 1: enable pwm1 from pin 108.
F81867 dec, 2011 v0.12p 294 4 pwm0_lpt_pin_en r/w 5vsb 0 0: disable pwm0 from pin 107. 1: enable pwm0 from pin 107. 3 pwm3_pin_en r/w 5vsb 0 0: disable pwm3 from pin 20. 1: enable pwm3 from pin 20. 2 pwm2_pin_en r/w 5vsb 0 0: disable pwm2 from pin 19. 1: enable pwm2 from pin 19. 1 pwm1_pin_en r/w 5vsb 0 0: disable pwm1 from pin 18. 1: enable pwm1 from pin 18. 0 pwm0_pin_en r/w 5vsb 0 0: disable pwm0 from pin 17. 1: enable pwm0 from pin 17. 10hz clock divisor low byte ? offset 2ah (available when clk_tune_prog_en = 1) bit name r/w reset default description 7-0 clk10hz_div r/w vbat 8?he7 the divisor of 10hz clock. internal 10hz clock is used to generate wdt event. it is divided from 10khz clock and could be fine tune by change its divisor. multi function select 3 register ? offset 2bh (available when clk_ tune_prog_en = 0) bit name r/w reset default description 7 gpio67_en r/w vbat 0 pin 87 function select 0: pin 87 functions as s5#. 1: pin 87 functions as gpio67. 6 gpio66_en r/w vbat 0 pin 86 function select 0: pin 86 functions as dpwrok. 1: pin 86 functions as gpio66. 5 gpio65_en r/w vbat 0 pin 74 function select 0: pin 74 functions as pme#. 1: pin 74 functions as gpio65. 4-2 reserved - - - reserved 1 fanin3_en r/w vbat 1 pin 102 function select 0: pin 102 functions as sclt. 1: pin 102 functions as fanin3. 0 fanctrl3_en r/w vbat 0 pin 103 function select. 0: pin 103 functions as gpio70/pe. 1: pin 103 functions as fanctrl3. 10hz clock fine tune count high byte ? offset 2bh (available when clk_ tune_prog_en = 1) bit name r/w reset default description 7 fine_tune_st - 5vsb - this bit indicates the fine tune mechanism is in process. 6-4 reserved - - - reserved 3-0 fine_tune_cnt r/w 5vsb 4?h3 this is the count of 10 cycles of internal 500khz clock with 48mhz clock.
F81867 dec, 2011 v0.12p 295 10hz clock fine tune count low byte ? offset 2ch (available when clk_ tune_prog_en = 1 bit name r/w reset default description 7-0 fine_tune_cnt r/w 5vsb 4?h3 this is the count of 10 cycles of internal 500khz clock with 48mhz clock. gpio0 enable register ? offset 2ch (available when clk_pr og_en = 0 and gpio_prog_sel = 2?b00) bit name r/w reset default description 7-5 reserved - - - reserved 4 gpio04_en r/w vbat 0 pin 56 function select. 0: pin 56 functions as slp_sus#. 1: pin 56 functions as gpio04. 3 gpio03_en r/w vbat 0 pin 55 function select. 0: pin 55 functions as sus_ack#. 1: pin 55 functions as gpio03. 2 gpio02_en r/w vbat 0 pin 54 function select. 0: pin 54 functions as sus_warn#. 1: pin 54 functions as gpio02. 1 gpio01_en r/w vbat 0 pin 53 function select. 0: pin 53 functions as erp_ctrl1#. 1: pin 53 functions as gpio01. 0 gpio00_en r/w vbat 0 pin 52 function select. 0: pin 52 functions as erp_ctrl0#. 1: pin 52 functions as gpio00. gpio1 enable register ? offset 2ch (available when clk_pr og_en = 0 and gpio_prog_sel = 2?b01) bit name r/w reset default description 7 gpio17_en r/w vbat 0 pin 72 function select. 0: pin 72 functions as peci. 1: pin 72 functions as gpio17. 6 gpio16_en r/w vbat 0 pin 71 function select. 0: pin 71 functions as beep. 1: pin 71 functions as gpio16. 5 gpio15_en r/w vbat 0 pin 70 function select. 0: pin 70 functions as wdtrst#. 1: pin 70 functions as gpio15. 4 reserved - - - reserved 3 gpio13_en r/w vbat 1 pin 68 function select. 0: pin 68 functions as irrx. 1: pin 68 functions as gpio13. if sda_pin68_en is set, pin 68 will function as sda.
F81867 dec, 2011 v0.12p 296 2 gpio12_en r/w vbat 1 pin 67 function select. 0: pin 67 functions as irtx. 1: pin 67 functions as gpio12. if scl_pin67_en is set, pin 67 will function as scl. 1 gpio11_en r/w vbat 1 pin 66 function select. 0: pin 66 functions as led_vcc. 1: pin 66 functions as gpio11. 0 gpio10_en r/w vbat 1 pin 65 function select. 0: pin 65 functions as led_vsb. 1: pin 65 functions as gpio10. gpio2 enable register ? offset 2ch (available when clk_pr og_en = 0 and gpio_prog_sel = 2?b10) bit name r/w reset default description 7 gpio27_en r/w vbat 0 pin 83 function select. 0: pin 83 functions as rsmrst#. 1: pin 83 functions as gpio27. 6 gpio26_en r/w vbat 0 pin 82 function select. 0: pin 82 functions as pwrok. 1: pin 82 functions as gpio26. 5 gpio25_en r/w vbat 0 pin 81 function select. 0: pin 81 functions as pson#. 1: pin 81 functions as gpio25. 4 gpio24_en r/w vbat 0 pin 80 function select. 0: pin 81 functions as s3#. 1: pin 81 functions as gpio24. 3 gpio23_en r/w vbat 0 pin 79 function select. 0: pin 68 functions as pwsout#. 1: pin 68 functions as gpio23. 2 gpio22_en r/w vbat 0 pin 78 function select. 0: pin 78 functions as pwsin#. 1: pin 78 functions as gpio22. 1 gpio21_en r/w vbat 0 pin 77 function select. 0: pin 77 functions as atxpg_in. 1: pin 77 functions as gpio21. 0 gpio20_en r/w vbat 0 pin 76 function select. 0: pin 76 functions as alert#. 1: pin 76 functions as gpio20. pin 76 will function as sc: if scl_pin76_en is set. c port enable register ? offset 2ch (available when clk_prog_en = 0 and gpio_prog_sel = 2?b11) bit name r/w reset default description 7 c_t2ex_en r/w vbat 0 set ?1? to enable c t2ex function from pin 16. 6 c_t2_en r/w vbat 0 set ?1? to enable c t2 function from pin 15.
F81867 dec, 2011 v0.12p 297 5 c_p35_en r/w vbat 0 set ?1? to enable c p3.5 (also function as c t1) function from pin 14. 4 c_p34_en r/w vbat 0 set ?1? to enable c p3.4 (also function as c t0) function from pin 13. 3 c_p33_en r/w vbat 0 set ?1? to enable c p3.3 (also function as c int1#) function from pin 12. 2 c_p32_en r/w vbat 0 set ?1? to enable c p3.2 (also function as c int0#) function from pin 9. 1 c_p31_en r/w vbat 0 set ?1? to enable c p3.1 (also function as c txd) function from pin 11. 0 c_p30_en r/w vbat 0 set ?1? to enable c p3.0 (also function as c rxd) function from pin 10. wakeup control register ? offset 2dh bit name r/w reset default description 7-5 reserved r/w - 0 reserved 4 key_sel_add r/w vbat 0 this bit is added to add more wakeup key function. 3 wakeup_en r/w vbat 1 0: disable keyboard/mouse wake up. 1: enable keyboard/mouse wake up. 2-1 key_sel r/w vbat 00 this registers select the keyboard wake up key. accompanying with key_sel_add, there are eight wakeup keys: key_sel_add key_sel wakeup key 0 00 ctrl + esc 0 01 ctrl + f1 0 10 ctrl + space 0 11 any key 1 00 windows wakeup 1 01 windows power 1 10 ctrl + alt + space 1 11 space 0 mo_sel r/w vbat 0 this register selects the mouse wake up key. 0: wake up by clicking. 1: wake up by clicking and movement. 7.20.14 ram c side register (base address 0x2500, 8 bytes) the 256 byte ram is accessed by base address + ram address.
F81867 dec, 2011 v0.12p 298 7.20.15 cir c side register (base address 0x2600, 256 bytes) cir ? cir fifo register ? index 2300h bit name r/w reset default description 7-0 cir_fifo r 5vsb 00h receiver buffer is read only register. when the cir pulse train has been detected and passed by the internal signal filter, the data sampled and shifted into shifter register will be written into receiver buffer register cir ? interrupt enable register ? index 2301h bit name r/w reset default description 7 interrupt_en r/w 5vsb 0b write 1 to enable cir interrupt. 6-0 reserved - - 00h reserved cir ? interrupt status register ? index 2302h bit name r/w reset default description 7-4 fifo_cnt r 5vsb 0h this nibble indicates the number of byte that rx data receive. 3 fifo_rst r/w 5vsb 0b write 1 to reset cir fifo. 2 reserved - - 0b reserved 1 data_lost r 5vsb 0b this bit indicates fifo data lost, and write 1 to clear this bit. 0 ready r 5vsb 0b this bit indicates rx data ready, and write 1 to clear this bit. cir ? baud rate low byte register ? index 2303h bit name r/w reset default description 7-0 baud_lo r/w 5vsb a5h the registers of bll are baud rate divisor latch. cir ? baud rate high byte register ? index 2304h bit name r/w reset default description 7-0 baud_hi r/w 5vsb 01h the registers of bhl are baud rate divisor latch. cir ? waveform logic 1 data register ? index 2305h bit name r/w reset default description 7-0 waveh r/w 5vsb 80h the registers of waveh indicate rx logic 1 waveform cir ? waveform logic 0 data register ? index 2306h bit name r/w reset default description 7-0 wavel r/w 5vsb 80h the registers of wavel indicate rx logic 0 count number cir ? waveform logic 1 count register ? index 2307h bit name r/w reset default description 7-0 waveh_count r/w 5vsb 04h the registers of waveh_count indicate rx logic 1 count number
F81867 dec, 2011 v0.12p 299 cir ? waveform logic 0 count register ? index 2308h bit name r/w reset default description 7-0 wavel_count r/w 5vsb 02h the registers of wavel_count indicate rx logic 0 count number cir ? rx protocol register ? index 2309h bit name r/w reset default description 7 low_frequency r/w 5vsb 1b write 1 to indicate rx carry frequency from 20k to 100k, and write 0 to indicate rx carry frequency from 400k to 500k. 6-5 reserved - - 0h reserved 4 rxinv r/w 5vsb 1b write 1 to indicate invert rx i nput, or to indicate by pass rx. 3 bypass r/w 5vsb 1b write 1 to indicate rx input is demo dulation , or to indicate rx is un-demodulation. 2-0 protocol r/w 5vsb 1h 000 : itt 001 : nec 010 : nokia 011 : sharp 100 : sony 101 : philips rc5 7.20.16 debug port c side register (base address 0x3200, 256 bytes) these registers are accessed by the host debug port interface, c can?t access these register. debug port control register ? offset 00h bit name r/w reset default description 7 soft_rst w 5vsb 0 debug port asserts a software reset to c. 6-4 reserved - - - reserved 3 dbport_exit_rst _en r/w 5vsb 0 set ?!? to enable reset c after exit debug mode. 2 dbport_step w 5vsb 0 write ?1? to trigger a single step. 1 dbport_next_br k w 5vsb 0 write ?1? to force c run to next break point. 0 dbport_free_ru n r/w 5vsb 0 0: c will stop when entering into the debug mode. 1: c is free run. break point select register ? offset 01h bit name r/w reset default description 7-2 reserved - - - reserved 1-0 brk_ptr_sel r/w - 5vsb 00h 00: select break point 0 to access. 01: select break point 1 to access. 10: select break point 2 to access. 11: select break point 3 to access.
F81867 dec, 2011 v0.12p 300 break point low register ? offset 02h bit name r/w reset default description 7-0 brk_ptr_lo r/w 5vsb 00h the low byte address of break point. break point high register ? offset 03h bit name r/w reset default description 7-0 brk_ptr_hi r/w 5vsb 00h the high byte address of break point. break point enable register ? offset + 05h bit name r/w reset default description 7-4 reserved - - - reserved 3 brk_ptr3_en r/w 5vsb 0 set ?1? to enable break point 3. c will stop when program counter match the programmed break points. 2 brk_ptr2_en r/w 5vsb 0 set ?1? to enable break point 2. c will stop when program counter match the programmed break points. 1 brk_ptr1_en r/w 5vsb 0 set ?1? to enable break point 1. c will stop when program counter match the programmed break points. 0 brk_ptr0_en r/w 5vsb 0 set ?1? to enable break point 0. c will stop when program counter match the programmed break points. debug port status register ? offset + 06h bit name r/w reset default description 7 dbport_entry r 5vsb - this bit will set ?1? when enter debug mode. 6 dbport_stop_ c r 5vsb - this bit will set ?1? when c stops. 5-3 reserved - - - reserved 2 dbport_step_st s r/w 5vsb 0 this bit will set after a single step operation. write ?1? to clear. 1 dbport_brk_sts r/w 5vsb 0 this bit will set when a break point matches. write ?1? to clear. 0 reserved - - - reserved debug port interrupt enable register ? offset + 07h bit name r/w reset default description 7 dbport_test_mo de r/w 5vsb 0 write ?1? to enable fintek test mode. 6-3 reserved - - - reserved 2 dbport_step_int _en r/w 5vsb 0 0: disable single step interrupt. 1: enable single step interrupt. 1 dbport_brk_int_ en r/w 5vsb 0 0: disalbe break point match interrupt. 1: enable break point match interrupt. brk_ptr_trig will be set when single step is end and dbport_step_int_en is set. or dbport_brk_int_en is set and a break point matches. 0 reserved - - - reserved
F81867 dec, 2011 v0.12p 301 debug port program count low register ? offset + 0ah bit name r/w reset default description 7-0 pc_lo r/w 5vsb 0 for write, this is the low byte of program counter written to c. it returns the current program counter low byte of c when read. debug port program count high register ? offset + 0ah bit name r/w reset default description 7-0 pc_hi r/w 5vsb 0 for write, this is the high byte of program counter written to c. it returns the current program counter high byte of c when read. the pc_hi and pc_lo will write to c?s program counter after writing this byte. debug port entry data register ? offset + 0fh bit name r/w reset default description 7-0 entry_data r/w 5vsb 0 to enter or exit debug mode, a sequence of data is needed to write to this byte. to enter the debug mode, the sequence is 0x19, 0x34, x010, 0x03. to exit the debug mode, the sequenc e is 0x30, 0x01, 0x43, 0x91.
F81867 dec, 2011 v0.12p 302 8. electrical characteristics 8.1 absolute maximum ratings parameter rating unit power supply voltage -0.5 to 5.5 v input voltage -0.5 to vdd+0.5 v operating temperature -40 to +85 (F81867-i) 0 to +70 (F81867) c storage temperature -55 to 150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device 8.2 dc characteristics (t a = 70 c, 3vcc = 3.3v 10%, gnd = 0v ) parameter conditions min typ max unit temperature error, remote diode 60 o c < t d < 100 o c, 3vcc = 3.0v to 3.6v 0 o c F81867 dec, 2011 v0.12p 303 input high voltage vih 2.0 v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v in st,5v -ttl level input pin with sch mitt trigger, 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v in t, u47, 5v -ttl level input pin, pull up 47k input low voltage vil 0.8 v input high voltage vih 2.0 v input high leakage ilih +1 a vin = vdd o 8 -output pin with 8 ma sink/source capability. output high current iol -8 ma voh = 2.4v output low current iol +8 ma vol = 0.4v o 12 -output pin with 12 ma sink/source capability. output high current iol -12 ma voh = 2.4v output low current iol +12 ma vol = 0.4v o 14 -output pin with 14 ma sink/source capability. output high current iol -14 ma voh = 2.4v output low current iol +14 ma vol = 0.4v o 16 -output pin with 16 ma sink/source capability. output high current iol -16 ma voh = 2.4v output low current iol +16 ma vol = 0.4v od 14,5v -open drain output pin with 14 ma sink capability, 5v tolerance. output low current iol +14 ma vol = 0.4v od 16,u10 -open drain output pin with 16 ma sink capability, internal 10k pull-up. output low current iol +16 ma vol = 0.4v od 12,5v -open drain output pin with 12 ma sink capability 5v tolerance. output low current iol +12 ma vol = 0.4v od 24t,5v -open drain output pin with 24 ma sink capability, 5v tolerance. output low current iol +24 ma vol = 0.4v ood 12, 5v - open drain or push pull by the register, with 12 ma sink/source capability, 5v tolerance. output high current iol -12 ma voh = 0.4v output low current iol +12 ma vol = 0.4v i/o 12st,5v -ttl level bi-directional pin with schmitt trigger, with 12 ma sink/source capability, 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v output high current iol -12 ma voh = 2.4v output low current iol +12 ma vol = 0.4v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v i/o 8st, 5v -ttl level bi-directional pin with schmitt trigge r, with 8 ma sink/source capability, 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v output high current iol -8 ma voh = 2.4v output low current iol +8 ma vol = 0.4v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v i/ood 12st, 5v -ttl level bi-directional pin with schmitt trigge r, output with 12 ma sink/source capability or open drain with 12ma sink capability, 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v
F81867 dec, 2011 v0.12p 304 output high current iol -12 ma voh = 2.4v output low current iol +12 ma vol = 0.4v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v i/ood 14st, 5v -ttl level bi-directional pin with schmitt trigge r, output with 14 ma sink/source capability or open drain with 14ma sink capability, 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v output high current iol -14 ma voh = 2.4v output low current iol +14 ma vol = 0.4v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v i/ood 8st, 5v -ttl level bi-directional pin with schmitt trigger, output with 8 ma sink/source capability or open drain with 8ma sink capability, 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v output high current iol -8 ma voh = 2.4v output low current iol +8 ma vol = 0.4v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v i/od 16st,5v -ttl level bi-directional pin with schmitt trigger, open drain output with16 ma sink capability, 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v output low current iol +16 ma vol = 0.4v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v i/od 12st, 5v - ttl level bi-directional pin with schmitt trigger, open drain output with 12ma source-sink capability, 5v tolerance. input low threshold voltage vt- 0.8 v input high threshold voltage vt+ 2.0 v output low current iol +12 ma vol = 0.4v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v i/o 16st - ttl level bi-directional pin and schmi tt trigger, 16 ma sink capability. input low threshold voltage vt- 0.8 v input high threshold voltage vt+ 2.0 v output high current ioh -16 ma voh = 2.4v output low current iol +16 ma vol = 0.4v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v
F81867 dec, 2011 v0.12p 305 9. ordering information 10. top marking specification the version identification is shown as the bold re d characters. please refer to below for detail: part number package type production flow F81867d-i 128-lqfp green package industrial, -40 c to +85 c F81867d 128-lqfp green package commercial, 0 c to +70 c 3 rd line: assembly plant code (x) + assembled year code (x ) + week code (xx) + fintek internal code (xx) + ic version (x) where a means version a, b means version b, ? F81867d xxxxxx x xxxxxx.xx fintek : pin 1 identifier 1 st line: fintek logo 2 nd line: F81867 d /F81867 d-i where d means the package code & -i means industrial spec. 4 th line: wafer fab code (xxxx?xx) F81867d-i xxxxxx x xxxxxx.xx fintek
F81867 dec, 2011 v0.12p 306 11. package dimensions 128 lqfp (14*14) feature integration technology inc. headquarters taipei office 3f-7, no 36, tai yuan st., bldg. k4, 7f, no.700, chung cheng rd., chupei city, hsinchu, taiwan 302, r.o.c. chungho city, taipei, taiwan 235, r.o.c. tel : 886-3-5600168 tel : 866-2-8227-8027 fax : 886-3-5600166 fax : 866-2-8227-8037 www: http://www.fintek.com.tw please note that all datasheet and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this datasheet belong to their respective owne r unit: mm
F81867 dec, 2011 v0.12p 307 12. application circuit tit le size document number rev date: sheet of F81867d feature integration technology inc. custom 18 tuesday , nov ember 08, 2011 vcc5v tr k0# (place the capcitor close to ic) vcc3v 1 2 c3 0.1u vcc3v vsb3v 1 2 c6 0.1u rdata# 1 2 c1 0.1u dcd2# 1 ri2# 2 cts2# 3 dtr2#/ovp_mode 4 rts2# 5 dsr2# 6 sout2 7 sin2 8 gpio50/densel#/rts6#/p3.2 9 gpio51/moa#/sin6/p3.0 10 gpio52/drva#/sout6/p3.1 11 gpio53/wdata#/dcd6#/p3.3 12 gpio54/dir#/ri6#/p3.4 13 gpio55/step#/cts6#/p3.5 14 gpio56/hdsel#/dtr6#/t2 15 gpio57/wgate#/dsr6#/t2ex 16 gpio60/rdata#/dcd5#/pwm0 17 gpio61/trk0#/ri5#/pwm1 18 gpio62/index#/cts5#/pwm2 19 gpio63/wpt#/dtr5#/pwm3 20 gpio64/dskchg#/dsr5# 21 gnd 22 lreset# 23 ldrq# 24 serirq 25 lframe# 26 lad0 27 lad1 28 lad2 29 lad3 30 3vcc 31 pciclk 32 clkin 33 kbrst# 34 ga20 35 dcd3#/gpio30 36 ri3#/gpio31 37 cts3#/gpio32 38 dtr3#/gpio33 39 rts3#/gpio34 40 dsr3#/gpio35 41 sout3/gpio36 42 sin3/gpio37 43 dcd4#/gpio40 44 ri4#/gpio41 45 cts4#/gpio42 46 dtr4#/gpio43 47 rts4#/gpio44 48 dsr4#/gpio45 49 sout4/gpio46 50 sin4/gpio47 51 erp_ctrl0#/gpio00 52 erp_ctrl1#/gpio01 53 sus_warn#/gpio02 54 sus_ack#/gpio03 55 slp_sus#/gpio04 56 gpio05/sout5 57 gpio06/sin5 58 gpio07/rts5# 59 i_vsb3v 60 mdata/scl 61 mclk/sd a 62 kdata 63 kclk 64 gpio/led_vsb 65 gpio11/led_vcc 66 scl/gpio12/irtx 67 sda/gpio13/trrx 68 gpio14/atx_at_trap 69 wdtrst#/gpio15 70 beep/gpio16/sda/cirrx# 71 peci/gpio17 72 5vsb(v5a) 73 pme#/gpio65 74 ovt# 75 alert#/gpio20/scl/cirrx# 76 atxpg_in/gpio21 77 pwsin#/gpio22 78 pwsout#/gpio23 79 s3#/gpio24 80 ps_on#/gpio25 81 pwok/gpio26 82 rsmrst#/gpio27 83 vbat 84 copen# 85 dpwrok/gpio66 86 s5#/gpio67 87 agnd 88 d- 89 d2+ 90 d1+(cpu) 91 vref 92 vin4 93 vin3 94 vin2 95 vin1(vcore) 96 3vsb 97 fanin1 98 fanctl1/pwm_dc1 99 fanin2 100 fanctl2/pwm_dc2 101 fanin3/slct 102 gpio70/pe/fanctl3/pwm_dc3 103 gpio71/busy 104 gpio72/ack# 105 gpio73/slin# 106 gpio74/init#/pwm0 107 gpio75/err#/pwm1 108 gpio76/afd#/pwm2 109 gpio77/stb#/pwm3 110 gpio80/pd0 111 gpio81/pd1 112 gpio82/pd2 113 gpio83/pd3 114 gpio84/pd4 115 gpio85/pd5 116 gpio86/pd6 117 gpio87/pd7 118 3vcc 119 dcd1# 120 ri1# 121 cts1# 122 dtr1#/fan_40_100 123 rts1#/conf ig4e_2e 124 dsr1# 125 sout1/i2c_addr 126 sin1 127 gnd 128 F81867d u1 F81867 5va wgate# hdsel# wdata# drva# moa# densel# step# dir# sout1 rts1# dtr1# r1 0 r106 10 1 2 c56 0.1u r10 560 pwrok rsmrst# rts1# gpio14 sout1 atxpg_in dtr1# r10 off: alarm mode on: force mode r11 off: atx mode on: at mode r12 off: fan 40% on: fan 100% r13 off: config 4e on: config 2e r14 off: 0x5c on: 0x5a r12 560 r13 560 r11 560 gpio14 power trip r r14 560 rsmrst# vsb3v pwrok vcc3v rsmrst# and pwrok pull up r8 4.7k r9 4.7k dtr2# s3# vsb5v pwsin# pwsout# alert# atxpg_in pme# ovt# peci wdtrst# beep irrx gpio14 led_vcc irtx led_vsb pciclk lad3 vcc3v lad1 lad2 lframe# lad0 ldrq# serirq wpt#/dtr5# dskchg#/dsr5# tr k0#/ r i 5# index#/cts5# rdata#/dcd5# 1 2 c81 0.1u decouple atx power supply noise. atxpg_in fanin1 fanctl1 fanin2 slct fanctl2 busy pe 1 2 c5 0.1u slin# ack# err# init# stb# afd# pd1 pd0 pd3 pd2 pd5 pd4 pd7 pd6 dcd1# cts1# ri1# rts1# dtr1# sout1 dsr1# sin1 ps_on# rsmrst# pwrok copen# s5# dpwrok d- d1+ d2+ vin4 vref vin2 vin3 vin1 dcd2# cts2# ri2# rts2# dtr2# sout2 dsr2# densel#/rts6# sin2 drva#/sout6 moa#/ si n 6 dir#/ri6# wdata#/dcd6# kdata kclk hdsel#/dtr6# step#/cts6# md ata mc lk wgate#/dsr6# rts5# sout5 sin5 sus_ack# slp_sus# erp_ctrl1# sus_warn# sin4 erp_ctrl0# dsr4# sout4 dtr4# rts4# ri4# cts4# sin3 dcd4# dsr3# sout3 dtr3# rts3# ri3# cts3# ga20 dcd3# clkin kbrst# lreset# d1 diode v3a vbat r7 0_x vsb3v dskchg# wpt# densel# moa# index# drva# dir# step# index# wpt# rdata# wdata# wgate# tr k0# dskchg# hdsel# vbat vcc3v 1 2 c4 0.1u 2 2 4 4 6 6 8 8 10 10 12 12 14 14 16 16 18 18 20 20 22 22 24 24 26 26 28 28 30 30 32 32 34 34 1 1 3 3 5 5 7 7 9 9 11 11 13 13 15 15 17 17 19 19 21 21 23 23 25 25 27 27 29 29 31 31 33 33 j1 header 17x2 1 2 c2 0.1u vbat r2 1k d2 diode r3 1k d3 diode r6 1k vsb3v r5 1k vbat r4 1k tr k0# index# dskchg# rdata# wpt# floppy
F81867 dec, 2011 v0.12p 308 (20-ssop) com1 +12v 1 ra1 2 ra2 3 ra3 4 dy1 5 dy2 6 ra4 7 dy3 8 ra5 9 -12v 10 gnd 11 ry5 12 da3 13 ry4 14 da2 15 da1 16 ry3 17 ry2 18 ry1 19 +5v 20 u2 gd75323 5 9 4 8 3 7 2 6 1 p1 uart db9 rin1 ri1# cts1# dtr1# sout1 rts1# dsr1# sin1 dcd1# -12v vcc5v +12v com2 (20-ssop) +12v 1 ra1 2 ra2 3 ra3 4 dy1 5 dy2 6 ra4 7 dy3 8 ra5 9 -12v 10 gnd 11 ry5 12 da3 13 ry4 14 da2 15 da1 16 ry3 17 ry2 18 ry1 19 +5v 20 u4 gd75323 5 9 4 8 3 7 2 6 1 p3 uart db9 -12v vcc5v ri2# +12v cts2# dtr2# sout2 rts2# dsr2# sin2 dcd2# (20-ssop) (20-ssop) com3 com4 +12v 1 ra1 2 ra2 3 ra3 4 dy1 5 dy2 6 ra4 7 dy3 8 ra5 9 -12v 10 gnd 11 ry5 12 da3 13 ry4 14 da2 15 da1 16 ry3 17 ry2 18 ry1 19 +5v 20 u6 gd75323 +12v 1 ra1 2 ra2 3 ra3 4 dy1 5 dy2 6 ra4 7 dy3 8 ra5 9 -12v 10 gnd 11 ry5 12 da3 13 ry4 14 da2 15 da1 16 ry3 17 ry2 18 ry1 19 +5v 20 u3 gd75323 5 9 4 8 3 7 2 6 1 p2 uart db9 5 9 4 8 3 7 2 6 1 p5 uart db9 vcc5v vcc5v -12v -12v +12v +12v ri4# ri3# dtr3# dtr4# cts4# cts3# rts3# rts4# sout4 sout3 sin3 sin4 dsr4# dsr3# dcd3# dcd4# com5 (20-ssop) +12v 1 ra1 2 ra2 3 ra3 4 dy1 5 dy2 6 ra4 7 dy3 8 ra5 9 -12v 10 gnd 11 ry5 12 da3 13 ry4 14 da2 15 da1 16 ry3 17 ry2 18 ry1 19 +5v 20 u5 gd75323 5 9 4 8 3 7 2 6 1 p4 uart db9 vcc5v +12v -12v w pt#/ d tr 5# trk0#/ri5# rts5# index#/cts5# sin5 sout5 rdata#/dcd5# dskchg#/dsr5# (20-ssop) com6 +12v 1 ra1 2 ra2 3 ra3 4 dy1 5 dy2 6 ra4 7 dy3 8 ra5 9 -12v 10 gnd 11 ry5 12 da3 13 ry4 14 da2 15 da1 16 ry3 17 ry2 18 ry1 19 +5v 20 u7 gd75323 5 9 4 8 3 7 2 6 1 p6 uart db9 -12v vcc5v dir#/ri6# +12v step#/cts6# hdsel#/dtr6# drva#/sout6 densel#/rts6# wgate#/dsr6# moa#/sin6 wdata#/dcd6# chipset_ri1# r15 8.2k r17 2.2k vsb3v r16 4.7k q1 npn c7 1000p d4 1n4148 rin1 wake up on ring for serial port circuit. tit le size document number rev date: sheet of F81867 feature integration technology inc. b 28 thursday , june 23, 2011
F81867 dec, 2011 v0.12p 309 title size document number rev date: sheet of F81867 feature integration technology inc. b 38 thursday , june 23, 2011 +vcc r26 10k 1 2 3 jp2 con3 r27 10k r28 3.6k d6 1n4148 3 2 1 8 4 + - u8a lm358 fanctl2 r25 27k r21 4.7k c11 47u nds0605/sot c10 0.1u fanin1 r23 100 1 2 3 4 jp1 4 header r20 4.7k r24 10k r22 27k +vcc d5 1n4148 c9 0.1u fanctl1 fanin2 +vcc r39 10k 1 2 3 jp4 con3 r40 10k r41 3.6k d8 1n4148 5 6 7 8 4 + - u8b lm358 r38 27k r35 4.7k c13 47u q4 nds0605/sot c15 0.1u slct r18 4.7k +vcc c14 0.1u r37 10k r30 4.7k r36 27k 2 1 3 q3 pnp r31 4.7k r29 4.7k r33 4.7k +vcc + c12 47u vcc5v 1 2 3 jp3 header 3 r19 10k r34 330 g d s q5 mosfet n 2n7002 d7 1n4148 r42 4.7k r49 10k 1 2 3 jp5 con3 r52 10k r54 3.6k d9 1n4148 3 2 1 8 4 + - u9a lm358 r48 27k r45 4.7k c16 47u q6 nds0605/sot c18 0.1u fanctl1 fanin2 c19 0.1u r53 10k r51 27k fanctl2 2 1 3 q7 pnp r44 4.7k r43 4.7k r47 4.7k +vcc + c17 47u 1 2 3 jp6 header 3 pwm fan1 speed control r50 330 g d s q8 mosfet n 2n7002 d10 1n4148 slct pwm fan3 speed control pe dc fan control with op 1 vcc3v r32 4.7k pe dc fan control with op 2 fanin1 r46 4.7k (four pin fan control) vcc3v pwm fan2 speed control + c8 47u fan control for pwm or dc dc fan control with op 3
F81867 dec, 2011 v0.12p 310 d11 led d12 led r56 2m copen# vbat c22 1000p case open circuit 1 2 sw1 sus_led led_vsb vsb3v vsb5v q11 npn r67 330 r68 4.7k led led_vcc p_led vsb5v vsb3v q10 npn r65 330 r66 4.7k r69 4.7k vcc3v ovt# ovt# pull-up tit le size document number rev date: sheet of F81867 F81867 dec, 2011 v0.12p 311 if you do not use the kbc, please pull-up these pin to vsb5v. vcc5v r76 4.7k c45 100p r77 4.7k f1 fuse c46 0.1u l1 fb l3 fb c44 100p ps2 mouse interface r78 4.7k l2 fb c47 100p c49 0.1u l4 fb c48 100p f2 fuse ps2 keyboard interface r79 4.7k 1 2 3 j3 con3 vsb5v mc lk md ata kclk kdata 6 4 2 1 3 5 js1 m-din_6-r 6 4 2 1 3 5 js2 m-din_6-r tit le size document number rev date: sheet of F81867 feature integration technology inc. b 58 thursday , june 23, 2011 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 j2 db25 1 2 3 4 5 6 7 8 rn3 2.7k-8p4r busy 1 2 3 4 5 6 7 8 rn1 2.7k-8p4r r75 2.7k vcc5v (female) slct 1 2 d13 1n5819 pe c33 180p busy c32 180p c36 180p c27 180p c37 180p c28 180p c38 180p c29 180p c39 180p c30 180p c40 180p c31 180p c41 180p c34 180p c42 180p c35 180p c43 180p ack# slct pe err# vcc3v slct busy pe ack# r70 4.7k err# r71 4.7k r72 4.7k r73 4.7k if you do not use the prarllel port , please pull-up these pin to vcc3v. r74 4.7k parallel port interface for lekage to power 1 2 3 4 5 6 7 8 rn5 33-8p4r 1 2 3 4 5 6 7 8 rn6 33-8p4r 1 2 3 4 5 6 7 8 rn7 33-8p4r 1 2 3 4 5 6 7 8 rn2 2.7k-8p4r 1 2 3 4 5 6 7 8 rn4 2.7k-8p4r pd0 slin# init# pd1 pd3 pd2 pd5 pd4 pd6 err# ack# pd7 afd# stb#
F81867 dec, 2011 v0.12p 312 tit le size document number rev date: sheet of F81867 feature integration technology inc. a 68 thursday , june 23, 2011 r80 300 r81 300 r82 100k vddio sda scl peci sid sic peci_client peci amdtsi (avoid pre-bios floating) client intel ibex r83 300 r84 300 vcc3v sda scl smlink[1]
F81867 dec, 2011 v0.12p 313 tit le size document number rev date: sheet of F81867 feature integration technology inc. b 78 thursday , june 23, 2011 v3a dpwrok r102 10k dsw pull up dsw slp_sus# r85 r sus_ack# slp_sus# r89 sus_warn# sus_ack# r92 r sus_warn# dpwrok r91 r sus_ack# dpwrok v3a r101 10k pson# pwsout# r90 1k pme# 5va r88 10k r87 10k 5vsb c52 10u c50 10u q12 mosfet p c51 1u erp_ctrl0# 5va 5vusb 5va r97 1k c55 10u c53 10u q13 mosfet p erp_ctrl1# c54 1u erp control vsb r95 10k r94 10k vsb3v erp acpi pull up pwsin# r86 10k r93 10k sus_warn# r96 0 sus_warn#(chipset) select sus_warn# to chipset or 5v_dual 5v_dual r100 10k r99 3k r98 0 q14 2n3904 q15 2n3904 r105 1k 5vsb r104 10k 3va r103 10k 5vdual_ctl sus_warn# 5vdual control
F81867 dec, 2011 v0.12p 314 tit le size document number rev date: sheet of f81866 feature integration technology inc. b 88 thursday , june 23, 2011 cpt pch sw2 wake event (g3')erp_ctrl1# (dsw)erp_ctrl0# 5va g3'_ctl dsw_ctl ps_in# erp block ps_on# ps_on# i_3vsb vbat 3vsb rsmrst# vcc_gate pme# pwrok 5vdual sus_warn# s5# s3# ri waek up event kb/ms rtc wake waek up event acpi block acpi block ldo3v atxpg_in d14 g3'_ctl atx_pg dsw_ctl 5vcc 5vsb_atx atx power supply F81867 ps_out# 3va 3vsb 5vsb sus_ack# sus_warn# 5vsb rsmrst# slp_sus# pwrbtn# slp_s4# slp_s3# pme# dpwrok dsw block slp_sus# sus_ack# sus_warn# dpwrok dsw block 3vldo en pwrok gpio27 dsw + fintek g3? mode
F81867 dec, 2011 v0.12p 315 fintek g3? (erp) mode

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